lpgbtfpga_deinterleaver.vhd
Go to the documentation of this file.
1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 
13 USE work.lpgbtfpga_package.all;
14 
20 ENTITY lpgbtfpga_deinterleaver IS
21  GENERIC(
22  DATARATE : integer RANGE 0 to 2;
23  FEC : integer RANGE 0 to 2
24  );
25  PORT (
26  -- Data
27  data_i : in std_logic_vector(255 downto 0);
28 
29  fec5_data_o : out std_logic_vector(233 downto 0);
30  fec5_fec_o : out std_logic_vector(19 downto 0);
31  fec12_data_o : out std_logic_vector(205 downto 0);
32  fec12_fec_o : out std_logic_vector(47 downto 0);
33 
34  -- Control
35  bypass : in std_logic
36  );
37 END lpgbtfpga_deinterleaver;
38 
43 ARCHITECTURE behavioral OF lpgbtfpga_deinterleaver IS
44 
45  SIGNAL fec5_data_5g12_s : std_logic_vector(233 downto 0);
46  SIGNAL fec5_fec_5g12_s : std_logic_vector(19 downto 0);
47 
48  SIGNAL fec5_data_10g24_s : std_logic_vector(233 downto 0);
49  SIGNAL fec5_fec_10g24_s : std_logic_vector(19 downto 0);
50 
51  SIGNAL fec12_data_5g12_s : std_logic_vector(205 downto 0);
52  SIGNAL fec12_fec_5g12_s : std_logic_vector(47 downto 0);
53 
54  SIGNAL fec12_data_10g24_s : std_logic_vector(205 downto 0);
55  SIGNAL fec12_fec_10g24_s : std_logic_vector(47 downto 0);
56 
57  SIGNAL fec5_data_s : std_logic_vector(233 downto 0);
58  SIGNAL fec5_fec_s : std_logic_vector(19 downto 0);
59  SIGNAL fec12_data_s : std_logic_vector(205 downto 0);
60  SIGNAL fec12_fec_s : std_logic_vector(47 downto 0);
61 
62 BEGIN --========#### Architecture Body ####========--
63 
64  fec5_gen: IF FEC = FEC5 GENERATE
65 
66  -- unused signals
67  fec12_data_s <= (others => '0');
68  fec12_fec_s <= (others => '0');
69  fec12_data_5g12_s <= (others => '0');
70  fec12_fec_5g12_s <= (others => '0');
71  fec12_data_10g24_s <= (others => '0');
72  fec12_fec_10g24_s <= (others => '0');
73 
74  fec5_5g12: IF DATARATE = DATARATE_5G12 GENERATE
75  -- unused signals
76  fec5_data_10g24_s <= (others => '0');
77  fec5_fec_10g24_s <= (others => '0');
78 
79  -- Code 0
80  fec5_data_5g12_s(116) <= '0';
81  fec5_data_5g12_s(115 downto 0) <= data_i(125 downto 10);
82  fec5_fec_5g12_s(9 downto 0) <= data_i(9 downto 0);
83 
84  -- Code 1 (Not USEd @5.12Gbps - THEN USEs 2nd phase of data)
85  fec5_data_5g12_s(233) <= '0';
86  fec5_data_5g12_s(232 downto 117) <= data_i(253 downto 138);
87  fec5_fec_5g12_s(19 downto 10) <= data_i(137 downto 128);
88 
89  END GENERATE;
90 
91  fec5_10g24: IF DATARATE = DATARATE_10G24 GENERATE
92  -- unused signals
93  fec5_data_5g12_s <= (others => '0');
94  fec5_fec_5g12_s <= (others => '0');
95 
96 
97  -- Code 0
98  fec5_data_10g24_s(233 downto 232) <= data_i(253 downto 252);
99  fec5_data_10g24_s(116 downto 0) <= data_i(251 downto 250) &
100  data_i(244 downto 240) &
101  data_i(234 downto 230) &
102  data_i(224 downto 220) &
103  data_i(214 downto 210) &
104  data_i(204 downto 200) &
105  data_i(194 downto 190) &
106  data_i(184 downto 180) &
107  data_i(174 downto 170) &
108  data_i(164 downto 160) &
109  data_i(154 downto 150) &
110  data_i(144 downto 140) &
111  data_i(134 downto 130) &
112  data_i(124 downto 120) &
113  data_i(114 downto 110) &
114  data_i(104 downto 100) &
115  data_i(94 downto 90) &
116  data_i(84 downto 80) &
117  data_i(74 downto 70) &
118  data_i(64 downto 60) &
119  data_i(54 downto 50) &
120  data_i(44 downto 40) &
121  data_i(34 downto 30) &
122  data_i(24 downto 20);
123 
124  fec5_fec_10g24_s(9 downto 0) <= data_i(14 downto 10) & data_i(4 downto 0);
125 
126  -- Code 1
127  fec5_data_10g24_s(231 downto 117) <= data_i(249 downto 245) &
128  data_i(239 downto 235) &
129  data_i(229 downto 225) &
130  data_i(219 downto 215) &
131  data_i(209 downto 205) &
132  data_i(199 downto 195) &
133  data_i(189 downto 185) &
134  data_i(179 downto 175) &
135  data_i(169 downto 165) &
136  data_i(159 downto 155) &
137  data_i(149 downto 145) &
138  data_i(139 downto 135) &
139  data_i(129 downto 125) &
140  data_i(119 downto 115) &
141  data_i(109 downto 105) &
142  data_i(99 downto 95) &
143  data_i(89 downto 85) &
144  data_i(79 downto 75) &
145  data_i(69 downto 65) &
146  data_i(59 downto 55) &
147  data_i(49 downto 45) &
148  data_i(39 downto 35) &
149  data_i(29 downto 25);
150 
151  fec5_fec_10g24_s(19 downto 10) <= data_i(19 downto 15) & data_i(9 downto 5);
152 
153  END GENERATE;
154 
155  -- Mux
156  fec5_data_s <= data_i(253 downto 20) WHEN bypass = '1' and (DATARATE = DATARATE_10G24) ELSE
157  fec5_data_5g12_s WHEN bypass = '1' ELSE
158  fec5_data_5g12_s WHEN DATARATE = DATARATE_5G12 ELSE
159  fec5_data_10g24_s;
160 
161  fec5_fec_s <= data_i(19 downto 0) WHEN bypass = '1' and (DATARATE = DATARATE_10G24) ELSE
162  fec5_fec_5g12_s WHEN bypass = '1' ELSE
163  fec5_fec_5g12_s WHEN DATARATE = DATARATE_5G12 ELSE
164  fec5_fec_10g24_s;
165 
166  END GENERATE;
167 
168  fec12_gen: IF FEC = FEC12 GENERATE
169  -- unused signals
170  fec5_data_s <= (others => '0');
171  fec5_fec_s <= (others => '0');
172  fec5_data_5g12_s <= (others => '0');
173  fec5_fec_5g12_s <= (others => '0');
174  fec5_data_10g24_s <= (others => '0');
175  fec5_fec_10g24_s <= (others => '0');
176 
177  fec12_5g12: IF DATARATE = DATARATE_5G12 GENERATE
178 
179  -- unused signals
180  fec12_data_10g24_s <= (others => '0');
181  fec12_fec_10g24_s <= (others => '0');
182 
183  -- Code 0
184  fec12_data_5g12_s(67 downto 66) <= data_i(123 downto 122);
185  fec12_data_5g12_s(33 downto 0) <= data_i(121 downto 120) &
186  data_i(111 downto 108) &
187  data_i(99 downto 96) &
188  data_i(87 downto 84) &
189  data_i(75 downto 72) &
190  data_i(63 downto 60) &
191  data_i(51 downto 48) &
192  data_i(39 downto 36) &
193  data_i(27 downto 24);
194 
195  -- Code 1
196  fec12_data_5g12_s(101 downto 100) <= data_i(125 downto 124);
197  fec12_data_5g12_s(65 downto 34) <= data_i(115 downto 112) &
198  data_i(103 downto 100) &
199  data_i(91 downto 88) &
200  data_i(79 downto 76) &
201  data_i(67 downto 64) &
202  data_i(55 downto 52) &
203  data_i(43 downto 40) &
204  data_i(31 downto 28);
205 
206  -- Code 2
207  fec12_data_5g12_s(99 downto 68) <= data_i(119 downto 116) &
208  data_i(107 downto 104) &
209  data_i(95 downto 92) &
210  data_i(83 downto 80) &
211  data_i(71 downto 68) &
212  data_i(59 downto 56) &
213  data_i(47 downto 44) &
214  data_i(35 downto 32);
215 
216  -- "Code 3, 4 & 5" : Duplicates code 0, 1 and 2 with second phase
217  fec12_data_5g12_s(169 downto 168) <= data_i(251 downto 250); -- Code 3
218  fec12_data_5g12_s(135 downto 102) <= data_i(249 downto 248) &
219  data_i(239 downto 236) &
220  data_i(227 downto 224) &
221  data_i(215 downto 212) &
222  data_i(203 downto 200) &
223  data_i(191 downto 188) &
224  data_i(179 downto 176) &
225  data_i(167 downto 164) &
226  data_i(155 downto 152);
227 
228  fec12_data_5g12_s(203 downto 202) <= data_i(253 downto 252); -- Code 4
229  fec12_data_5g12_s(167 downto 136) <= data_i(243 downto 240) &
230  data_i(231 downto 228) &
231  data_i(219 downto 216) &
232  data_i(207 downto 204) &
233  data_i(195 downto 192) &
234  data_i(183 downto 180) &
235  data_i(171 downto 168) &
236  data_i(159 downto 156);
237 
238  fec12_data_5g12_s(201 downto 170) <= data_i(247 downto 244) & -- Code 5
239  data_i(235 downto 232) &
240  data_i(223 downto 220) &
241  data_i(211 downto 208) &
242  data_i(199 downto 196) &
243  data_i(187 downto 184) &
244  data_i(175 downto 172) &
245  data_i(163 downto 160);
246 
247  -- FEC 0, 1 & 2
248  fec12_fec_5g12_s(23 downto 0) <= data_i(23 downto 20) &
249  data_i(11 downto 8) &
250  data_i(19 downto 16) &
251  data_i(7 downto 4) &
252  data_i(15 downto 12) &
253  data_i(3 downto 0);
254 
255  -- FEC 3, 4 & 5: Duplicates FEC 0, 1 and 2 with second phase
256  fec12_fec_5g12_s(47 downto 24) <= data_i(151 downto 148) &
257  data_i(139 downto 136) &
258  data_i(147 downto 144) &
259  data_i(135 downto 132) &
260  data_i(143 downto 140) &
261  data_i(131 downto 128);
262 
263  END GENERATE;
264 
265  fec12_10g24: IF DATARATE = DATARATE_10G24 GENERATE
266 
267  -- unused signals
268  fec12_data_5g12_s <= (others => '0');
269  fec12_fec_5g12_s <= (others => '0');
270 
271  -- Code 0
272  fec12_data_10g24_s(135 downto 134) <= data_i(243 downto 242);
273  fec12_data_10g24_s(33 downto 0) <= data_i(241 downto 240) &
274  data_i(219 downto 216) &
275  data_i(195 downto 192) &
276  data_i(171 downto 168) &
277  data_i(147 downto 144) &
278  data_i(123 downto 120) &
279  data_i(99 downto 96) &
280  data_i(75 downto 72) &
281  data_i(51 downto 48);
282 
283  -- Code 1
284  fec12_data_10g24_s(169 downto 168) <= data_i(247 downto 246);
285  fec12_data_10g24_s(67 downto 34) <= data_i(245 downto 244) &
286  data_i(223 downto 220) &
287  data_i(199 downto 196) &
288  data_i(175 downto 172) &
289  data_i(151 downto 148) &
290  data_i(127 downto 124) &
291  data_i(103 downto 100) &
292  data_i(79 downto 76) &
293  data_i(55 downto 52);
294 
295  -- Code 2
296  fec12_data_10g24_s(203 downto 202) <= data_i(251 downto 250);
297  fec12_data_10g24_s(101 downto 68) <= data_i(249 downto 248) &
298  data_i(227 downto 224) &
299  data_i(203 downto 200) &
300  data_i(179 downto 176) &
301  data_i(155 downto 152) &
302  data_i(131 downto 128) &
303  data_i(107 downto 104) &
304  data_i(83 downto 80) &
305  data_i(59 downto 56);
306 
307  -- Code 3
308  fec12_data_10g24_s(205 downto 204) <= data_i(253 downto 252);
309  fec12_data_10g24_s(133 downto 102) <= data_i(231 downto 228) &
310  data_i(207 downto 204) &
311  data_i(183 downto 180) &
312  data_i(159 downto 156) &
313  data_i(135 downto 132) &
314  data_i(111 downto 108) &
315  data_i(87 downto 84) &
316  data_i(63 downto 60);
317 
318  -- Code 4
319  fec12_data_10g24_s(167 downto 136) <= data_i(235 downto 232) &
320  data_i(211 downto 208) &
321  data_i(187 downto 184) &
322  data_i(163 downto 160) &
323  data_i(139 downto 136) &
324  data_i(115 downto 112) &
325  data_i(91 downto 88) &
326  data_i(67 downto 64);
327 
328  -- Code 5
329  fec12_data_10g24_s(201 downto 170) <= data_i(239 downto 236) &
330  data_i(215 downto 212) &
331  data_i(191 downto 188) &
332  data_i(167 downto 164) &
333  data_i(143 downto 140) &
334  data_i(119 downto 116) &
335  data_i(95 downto 92) &
336  data_i(71 downto 68);
337 
338  fec12_fec_10g24_s <= data_i(47 downto 44) &
339  data_i(23 downto 20) &
340  data_i(43 downto 40) &
341  data_i(19 downto 16) &
342  data_i(39 downto 36) &
343  data_i(15 downto 12) &
344  data_i(35 downto 32) &
345  data_i(11 downto 8) &
346  data_i(31 downto 28) &
347  data_i(7 downto 4) &
348  data_i(27 downto 24) &
349  data_i(3 downto 0);
350 
351  END GENERATE;
352 
353  -- Mux
354  fec12_data_s <= data_i(253 downto 48) WHEN bypass = '1' and (DATARATE = DATARATE_10G24) ELSE
355  '0' & data_i (253 downto 152) & '0' & data_i(125 downto 24) WHEN bypass = '1' ELSE
356  fec12_data_5g12_s WHEN DATARATE = DATARATE_5G12 ELSE
357  fec12_data_10g24_s;
358 
359  fec12_fec_s <= data_i(47 downto 0) WHEN bypass = '1' and (DATARATE = DATARATE_10G24) ELSE
360  data_i(151 downto 128) & data_i(23 downto 0) WHEN bypass = '1' ELSE
361  fec12_fec_5g12_s WHEN DATARATE = DATARATE_5G12 ELSE
362  fec12_fec_10g24_s;
363 
364  END GENERATE;
365 
366  fec5_data_o <= fec5_data_s WHEN FEC = FEC5 ELSE (OTHERS => '0');
367  fec5_fec_o <= fec5_fec_s WHEN FEC = FEC5 ELSE (OTHERS => '0');
368 
369  fec12_data_o <= fec12_data_s WHEN FEC = FEC12 ELSE (OTHERS => '0');
370  fec12_fec_o <= fec12_fec_s WHEN FEC = FEC12 ELSE (OTHERS => '0');
371 
372 END behavioral;
373 --=================================================================================================--
374 --#################################################################################################--
375 --=================================================================================================--
lpgbtfpga_deinterleaver.behavioral.fec5_data_5g12_s
std_logic_vector%(%233%%%downto%%%0%)% fec5_data_5g12_s
Data output for 5.12Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:45
lpgbtfpga_deinterleaver.fec5_fec_o
out fec5_fec_ostd_logic_vector%(%19%%%downto%%%0%)
Output FEC for FEC5 encoding (data is duplicated in upper/lower part of the frame @5...
Definition: lpgbtfpga_deinterleaver.vhd:30
lpgbtfpga_deinterleaver.fec12_fec_o
out fec12_fec_ostd_logic_vector%(%47%%%downto%%%0%)
Output FEC for FEC12 encoding (data is duplicated in upper/lower part of the frame @5...
Definition: lpgbtfpga_deinterleaver.vhd:32
lpgbtfpga_deinterleaver.data_i
in data_istd_logic_vector%(%255%%%downto%%%0%)
Input frame from the Rx gearbox (data shall be duplicated in upper/lower part of the frame @5...
Definition: lpgbtfpga_deinterleaver.vhd:27
lpgbtfpga_deinterleaver.behavioral.fec5_data_s
std_logic_vector%(%233%%%downto%%%0%)% fec5_data_s
FEC5 data from de-interleaver.
Definition: lpgbtfpga_deinterleaver.vhd:57
lpgbtfpga_decoder.ieee
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.
Definition: lpgbtfpga_decoder.vhd:9
lpgbtfpga_deinterleaver.DATARATE
DATARATEinteger%range%0%%%to%%%2
Datarate selection can be: DATARATE_10G24 or DATARATE_5G12.
Definition: lpgbtfpga_deinterleaver.vhd:22
lpgbtfpga_deinterleaver.behavioral.fec5_data_10g24_s
std_logic_vector%(%233%%%downto%%%0%)% fec5_data_10g24_s
Data output for 10.24Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:48
lpgbtfpga_deinterleaver.FEC
FECinteger%range%0%%%to%%%2
FEC selection can be: FEC5 or FEC12.
Definition: lpgbtfpga_deinterleaver.vhd:23
lpgbtfpga_deinterleaver
lpgbtfpga_deinterleaver - Uplink data de-interleaver
Definition: lpgbtfpga_deinterleaver.vhd:20
lpgbtfpga_deinterleaver.behavioral.fec5_fec_5g12_s
std_logic_vector%(%19%%%downto%%%0%)% fec5_fec_5g12_s
FEC output for 5.12Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:46
lpgbtfpga_package
Definition: lpgbtfpga_package.vhd:13
lpgbtfpga_deinterleaver.bypass
in bypassstd_logic%
Bypass uplink interleaver (test purpose only)
Definition: lpgbtfpga_deinterleaver.vhd:35
lpgbtfpga_deinterleaver.behavioral.fec12_fec_5g12_s
std_logic_vector%(%47%%%downto%%%0%)% fec12_fec_5g12_s
FEC output for 5.12Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:52
lpgbtfpga_deinterleaver.behavioral.fec12_data_s
std_logic_vector%(%205%%%downto%%%0%)% fec12_data_s
FEC12 data from de-interleaver.
Definition: lpgbtfpga_deinterleaver.vhd:59
lpgbtfpga_deinterleaver.behavioral.fec12_fec_s
std_logic_vector%(%47%%%downto%%%0%)% fec12_fec_s
FEC12 FEC from de-interleaver.
Definition: lpgbtfpga_deinterleaver.vhd:60
lpgbtfpga_deinterleaver.behavioral.fec12_data_5g12_s
std_logic_vector%(%205%%%downto%%%0%)% fec12_data_5g12_s
Data output for 5.12Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:51
lpgbtfpga_deinterleaver.behavioral.fec5_fec_10g24_s
std_logic_vector%(%19%%%downto%%%0%)% fec5_fec_10g24_s
FEC output for 10.24Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:49
lpgbtfpga_deinterleaver.behavioral.fec12_fec_10g24_s
std_logic_vector%(%47%%%downto%%%0%)% fec12_fec_10g24_s
FEC output for 10.24Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:55
lpgbtfpga_deinterleaver.behavioral.fec5_fec_s
std_logic_vector%(%19%%%downto%%%0%)% fec5_fec_s
FEC5 FEC from de-interleaver.
Definition: lpgbtfpga_deinterleaver.vhd:58
lpgbtfpga_deinterleaver.fec12_data_o
out fec12_data_ostd_logic_vector%(%205%%%downto%%%0%)
Output data for FEC12 encoding (data is duplicated in upper/lower part of the frame @5...
Definition: lpgbtfpga_deinterleaver.vhd:31
lpgbtfpga_deinterleaver.fec5_data_o
out fec5_data_ostd_logic_vector%(%233%%%downto%%%0%)
Output data for FEC5 encoding (data is duplicated in upper/lower part of the frame @5...
Definition: lpgbtfpga_deinterleaver.vhd:29
lpgbtfpga_deinterleaver.behavioral.fec12_data_10g24_s
std_logic_vector%(%205%%%downto%%%0%)% fec12_data_10g24_s
Data output for 10.24Gbps configuration.
Definition: lpgbtfpga_deinterleaver.vhd:54
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