lpgbtfpga_deinterleaver Entity Reference

lpgbtfpga_deinterleaver - Uplink data de-interleaver More...

Inheritance diagram for lpgbtfpga_deinterleaver:
lpgbtfpga_uplink

Detailed Description

lpgbtfpga_deinterleaver - Uplink data de-interleaver

De-interleaves the data to extract the encoded message from the received frame. Interleaving data improves the decoding efficiency by increasing the number of consecutive bits with errors that can be corrected.

Definition at line 20 of file lpgbtfpga_deinterleaver.vhd.


The documentation for this class was generated from the following file:

Entities

behavioral  architecture
 lpgbtfpga_deinterleaver - Uplink data de-interleaver More...
 

Libraries

ieee 
 Include the IEEE VHDL standard LIBRARY.

Use Clauses

ieee.std_logic_1164.all 
work.lpgbtfpga_package.all 
 Include the lpGBT-FPGA specific package.

Generics

DATARATE  integer range 0 to 2
 Datarate selection can be: DATARATE_10G24 or DATARATE_5G12.
FEC  integer range 0 to 2
 FEC selection can be: FEC5 or FEC12.

Ports

data_i   in std_logic_vector ( 255 downto 0 )
 Input frame from the Rx gearbox (data shall be duplicated in upper/lower part of the frame @5.12Gbps)
fec5_data_o   out std_logic_vector ( 233 downto 0 )
 Output data for FEC5 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
fec5_fec_o   out std_logic_vector ( 19 downto 0 )
 Output FEC for FEC5 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
fec12_data_o   out std_logic_vector ( 205 downto 0 )
 Output data for FEC12 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
fec12_fec_o   out std_logic_vector ( 47 downto 0 )
 Output FEC for FEC12 encoding (data is duplicated in upper/lower part of the frame @5.12Gbps)
bypass   in std_logic
 Bypass uplink interleaver (test purpose only)