lpgbtfpga_decoder.vhd
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1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 
13 USE work.lpgbtfpga_package.all;
14 
20  GENERIC(
21  DATARATE : integer RANGE 0 TO 2;
22  FEC : integer RANGE 0 TO 2
23  );
24  PORT (
25  -- Clock
26  uplinkClk_i : in std_logic;
27  uplinkClkOutEn_i : in std_logic;
28 
29  -- Data
30  fec5_data_i : in std_logic_vector(233 downto 0);
31  fec5_fec_i : in std_logic_vector(19 downto 0);
32  fec12_data_i : in std_logic_vector(205 downto 0);
33  fec12_fec_i : in std_logic_vector(47 downto 0);
34 
35  fec5_data_o : out std_logic_vector(233 downto 0);
36  fec12_data_o : out std_logic_vector(205 downto 0);
37 
38  fec5_correction_pattern_o : out std_logic_vector(233 downto 0);
39  fec12_correction_pattern_o : out std_logic_vector(205 downto 0);
40 
41  -- Control
42  bypass : in std_logic
43  );
44 END lpgbtfpga_decoder;
45 
50 ARCHITECTURE behavioral OF lpgbtfpga_decoder IS
51 
52 
53  -- N31K29 decoder component
54  COMPONENT rs_decoder_N31K29
55  GENERIC (
56  N : integer := 31;
57  K : integer := 29;
58  SYMB_BITWIDTH : integer := 5
59  );
60  PORT (
61  payloadData_i : in std_logic_vector((K*SYMB_BITWIDTH)-1 downto 0);
62  fecData_i : in std_logic_vector(((N-K)*SYMB_BITWIDTH)-1 downto 0);
63 
64  data_o : out std_logic_vector((K*SYMB_BITWIDTH)-1 downto 0)
65  );
66  END COMPONENT;
67 
68  -- N15K13 decoder component
69  COMPONENT rs_decoder_N15K13
70  GENERIC (
71  N : integer := 15;
72  K : integer := 13;
73  SYMB_BITWIDTH : integer := 4
74  );
75  PORT (
76  payloadData_i : in std_logic_vector((K*SYMB_BITWIDTH)-1 downto 0);
77  fecData_i : in std_logic_vector(((N-K)*SYMB_BITWIDTH)-1 downto 0);
78 
79  data_o : out std_logic_vector((K*SYMB_BITWIDTH)-1 downto 0)
80  );
81  END COMPONENT;
82 
83  -- Signals
84  SIGNAL fec5_encoded_code0_s : std_logic_vector(144 downto 0);
85  SIGNAL fec5_encoded_code1_s : std_logic_vector(144 downto 0);
86 
87  SIGNAL fec5_decoded_code0_s : std_logic_vector(144 downto 0);
88  SIGNAL fec5_decoded_code1_s : std_logic_vector(144 downto 0);
89 
90  SIGNAL fec12_encoded_code0_s : std_logic_vector(51 downto 0);
91  SIGNAL fec12_encoded_code1_s : std_logic_vector(51 downto 0);
92  SIGNAL fec12_encoded_code2_s : std_logic_vector(51 downto 0);
93  SIGNAL fec12_encoded_code3_s : std_logic_vector(51 downto 0);
94  SIGNAL fec12_encoded_code4_s : std_logic_vector(51 downto 0);
95  SIGNAL fec12_encoded_code5_s : std_logic_vector(51 downto 0);
96 
97  SIGNAL fec12_decoded_code0_s : std_logic_vector(51 downto 0);
98  SIGNAL fec12_decoded_code1_s : std_logic_vector(51 downto 0);
99  SIGNAL fec12_decoded_code2_s : std_logic_vector(51 downto 0);
100  SIGNAL fec12_decoded_code3_s : std_logic_vector(51 downto 0);
101  SIGNAL fec12_decoded_code4_s : std_logic_vector(51 downto 0);
102  SIGNAL fec12_decoded_code5_s : std_logic_vector(51 downto 0);
103 
104  SIGNAL fec5_data_s : std_logic_vector(233 downto 0);
105  SIGNAL fec5_toenc_data_s : std_logic_vector(233 downto 0);
106  SIGNAL fec12_data_s : std_logic_vector(205 downto 0);
107  SIGNAL fec12_toenc_data_s : std_logic_vector(205 downto 0);
108 
109 BEGIN --========#### Architecture Body ####========--
110 
111  -- FEC5 decoders
112  fec5_dec_gen: IF FEC = FEC5 GENERATE
113 
114  fec5_encoded_code0_s <= "00000000000000000000000000" &
115  fec5_data_i(233 downto 232) &
116  fec5_data_i(116 downto 0) WHEN (DATARATE = DATARATE_10G24) ELSE
117  "00000000000000000000000000000" &
118  fec5_data_i(115 downto 0);
119 
120  rs_decoder_N31K29_c0_inst: rs_decoder_N31K29
121  PORT MAP (
123  fecData_i => fec5_fec_i(9 downto 0),
124 
126  );
127 
128  dec10g24_fec5_gen: IF DATARATE = DATARATE_10G24 GENERATE
129 
130  fec5_encoded_code1_s <= "000000000000000000000000000000" & fec5_data_i(231 downto 117) WHEN (DATARATE = DATARATE_10G24) ELSE
131  "00000000000000000000000000000" & fec5_data_i(231 downto 116);
132 
133  rs_decoder_N31K29_c1_inst: rs_decoder_N31K29
134  PORT MAP (
136  fecData_i => fec5_fec_i(19 downto 10),
137 
139  );
140 
141  END GENERATE;
142 
143  dec5g12_fec5_gen: IF DATARATE = DATARATE_5G12 GENERATE
144  fec5_decoded_code1_s <= (OTHERS => '0');
145  END GENERATE;
146 
147  END GENERATE;
148 
149  -- FEC12 decoders
150  fec12_dec_gen: IF FEC = FEC12 GENERATE
151 
152  fec12_encoded_code0_s <= "0000000000000000" & fec12_data_i(135 downto 134) & fec12_data_i(33 downto 0) WHEN (DATARATE = DATARATE_10G24) ELSE
153  "0000000000000000" & fec12_data_i(67 downto 66) & fec12_data_i(33 downto 0);
154 
155  fec12_encoded_code1_s <= "0000000000000000" & fec12_data_i(169 downto 168) & fec12_data_i(67 downto 34) WHEN (DATARATE = DATARATE_10G24) ELSE
156  "000000000000000000" & fec12_data_i(101 downto 100) & fec12_data_i(65 downto 34);
157 
158  fec12_encoded_code2_s <= "0000000000000000" & fec12_data_i(203 downto 202) & fec12_data_i(101 downto 68) WHEN (DATARATE = DATARATE_10G24) ELSE
159  "00000000000000000000" & fec12_data_i(99 downto 68);
160 
161  rs_decoder_N15K13_c0_inst: rs_decoder_N15K13
162  PORT MAP (
164  fecData_i => fec12_fec_i(7 downto 0),
165 
167  );
168 
169  rs_decoder_N15K13_c1_inst: rs_decoder_N15K13
170  PORT MAP (
172  fecData_i => fec12_fec_i(15 downto 8),
173 
175  );
176 
177  rs_decoder_N15K13_c2_inst: rs_decoder_N15K13
178  PORT MAP (
180  fecData_i => fec12_fec_i(23 downto 16),
181 
183  );
184 
185  dec5g12_fec12_gen: IF DATARATE = DATARATE_5G12 GENERATE
186  fec12_decoded_code3_s <= (OTHERS => '0');
187  fec12_decoded_code4_s <= (OTHERS => '0');
188  fec12_decoded_code5_s <= (OTHERS => '0');
189  END GENERATE;
190 
191  dec10g24_fec12_gen: IF DATARATE = DATARATE_10G24 GENERATE
192 
193  fec12_encoded_code3_s <= "000000000000000000" & fec12_data_i(205 downto 204) & fec12_data_i(133 downto 102) WHEN (DATARATE = DATARATE_10G24) ELSE
194  "0000000000000000" & fec12_data_i(169 downto 168) & fec12_data_i(135 downto 102);
195 
196  fec12_encoded_code4_s <= "00000000000000000000" & fec12_data_i(167 downto 136) WHEN (DATARATE = DATARATE_10G24) ELSE
197  "000000000000000000" & fec12_data_i(203 downto 202) & fec12_data_i(167 downto 136);
198 
199  fec12_encoded_code5_s <= "00000000000000000000" & fec12_data_i(201 downto 170) WHEN (DATARATE = DATARATE_10G24) ELSE
200  "00000000000000000000" & fec12_data_i(201 downto 170);
201 
202  rs_decoder_N15K13_c3_inst: rs_decoder_N15K13
203  PORT MAP (
205  fecData_i => fec12_fec_i(31 downto 24),
206 
208  );
209 
210  rs_decoder_N15K13_c4_inst: rs_decoder_N15K13
211  PORT MAP (
213  fecData_i => fec12_fec_i(39 downto 32),
214 
216  );
217 
218  rs_decoder_N15K13_c5_inst: rs_decoder_N15K13
219  PORT MAP (
221  fecData_i => fec12_fec_i(47 downto 40),
222 
224  );
225  END GENERATE;
226 
227  END GENERATE;
228 
229  -- If FEC5 is disabled, force value to 0
230  fec5_dec_dis_gen: IF FEC = FEC12 GENERATE
231  fec5_decoded_code0_s <= (OTHERS => '0');
232  fec5_decoded_code1_s <= (OTHERS => '0');
233 
234  fec5_encoded_code0_s <= (OTHERS => '0');
235  fec5_encoded_code1_s <= (OTHERS => '0');
236  END GENERATE;
237 
238  -- If FEC12 is disabled, force value to 0
239  fec12_dec_dis_gen: IF FEC = FEC5 GENERATE
240  fec12_decoded_code0_s <= (OTHERS => '0');
241  fec12_decoded_code1_s <= (OTHERS => '0');
242  fec12_decoded_code2_s <= (OTHERS => '0');
243  fec12_decoded_code3_s <= (OTHERS => '0');
244  fec12_decoded_code4_s <= (OTHERS => '0');
245  fec12_decoded_code5_s <= (OTHERS => '0');
246 
247  fec12_encoded_code0_s <= (OTHERS => '0');
248  fec12_encoded_code1_s <= (OTHERS => '0');
249  fec12_encoded_code2_s <= (OTHERS => '0');
250  fec12_encoded_code3_s <= (OTHERS => '0');
251  fec12_encoded_code4_s <= (OTHERS => '0');
252  fec12_encoded_code5_s <= (OTHERS => '0');
253  END GENERATE;
254 
255  PROCESS(uplinkClk_i)
256  BEGIN
257  IF rising_edge(uplinkClk_i) THEN
258  IF uplinkClkOutEn_i = '1' THEN
259  fec5_correction_pattern_o <= fec5_toenc_data_s xor fec5_data_s;
260  fec12_correction_pattern_o <= fec12_toenc_data_s xor fec12_data_s;
261  END IF;
262  END IF;
263  END PROCESS;
264 
267 
268  fec5_data_s <= fec5_data_i WHEN bypass = '1' ELSE
269  fec5_decoded_code0_s(118 downto 117) &
270  fec5_decoded_code1_s(114 downto 0) &
271  fec5_decoded_code0_s(116 downto 0) WHEN DATARATE = DATARATE_10G24 ELSE
272  '0' & fec5_decoded_code1_s(115 downto 0) &
273  '0' & fec5_decoded_code0_s(115 downto 0);
274 
275  fec12_data_s <= fec12_data_i WHEN bypass = '1' ELSE
276  fec12_decoded_code3_s(33 downto 32) &
277  fec12_decoded_code2_s(35 downto 34) &
278  fec12_decoded_code5_s(31 downto 0) &
279  fec12_decoded_code1_s(35 downto 34) &
280  fec12_decoded_code4_s(31 downto 0) &
281  fec12_decoded_code0_s(35 downto 34) &
282  fec12_decoded_code3_s(31 downto 0) &
283  fec12_decoded_code2_s(33 downto 0) &
284  fec12_decoded_code1_s(33 downto 0) &
285  fec12_decoded_code0_s(33 downto 0) WHEN DATARATE = DATARATE_10G24 ELSE
286  '0' &
287  fec12_decoded_code4_s(33 downto 32) &
288  fec12_decoded_code5_s(31 downto 0) &
289  fec12_decoded_code3_s(35 downto 34) &
290  fec12_decoded_code4_s(31 downto 0) &
291  fec12_decoded_code3_s(33 downto 0) &
292  '0' &
293  fec12_decoded_code1_s(33 downto 32) &
294  fec12_decoded_code2_s(31 downto 0) &
295  fec12_decoded_code0_s(35 downto 34) &
296  fec12_decoded_code1_s(31 downto 0) &
297  fec12_decoded_code0_s(33 downto 0);
298 
299  fec5_toenc_data_s <= fec5_data_i WHEN bypass = '1' ELSE
300  fec5_encoded_code0_s(118 downto 117) &
301  fec5_encoded_code1_s(114 downto 0) &
302  fec5_encoded_code0_s(116 downto 0) WHEN DATARATE = DATARATE_10G24 ELSE
303  '0' & fec5_encoded_code1_s(115 downto 0) &
304  '0' & fec5_encoded_code0_s(115 downto 0);
305 
306  fec12_toenc_data_s <= fec12_data_i WHEN bypass = '1' ELSE
307  fec12_encoded_code3_s(33 downto 32) &
308  fec12_encoded_code2_s(35 downto 34) &
309  fec12_encoded_code5_s(31 downto 0) &
310  fec12_encoded_code1_s(35 downto 34) &
311  fec12_encoded_code4_s(31 downto 0) &
312  fec12_encoded_code0_s(35 downto 34) &
313  fec12_encoded_code3_s(31 downto 0) &
314  fec12_encoded_code2_s(33 downto 0) &
315  fec12_encoded_code1_s(33 downto 0) &
316  fec12_encoded_code0_s(33 downto 0) WHEN DATARATE = DATARATE_10G24 ELSE
317  '0' &
318  fec12_encoded_code4_s(33 downto 32) &
319  fec12_encoded_code5_s(31 downto 0) &
320  fec12_encoded_code3_s(35 downto 34) &
321  fec12_encoded_code4_s(31 downto 0) &
322  fec12_encoded_code3_s(33 downto 0) &
323  '0' &
324  fec12_encoded_code1_s(33 downto 32) &
325  fec12_encoded_code2_s(31 downto 0) &
326  fec12_encoded_code0_s(35 downto 34) &
327  fec12_encoded_code1_s(31 downto 0) &
328  fec12_encoded_code0_s(33 downto 0);
329 
330 END behavioral;
331 --=================================================================================================--
332 --#################################################################################################--
333 --=================================================================================================--
std_logic_vector%(%233%%%downto%%%0%)% fec5_toenc_data_s
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code0_s
FEC12 decoded data (code 0)
std_logic_vector%(%233%%%downto%%%0%)% fec5_data_s
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code2_s
FEC12 decoded data (code 2)
rs_decoder_N15K13 - N15K13 Reed-Solomon decoder
in payloadData_istd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Message to be decoded.
std_logic_vector%(%144%%%downto%%%0%)% fec5_decoded_code1_s
FEC5 decoded data (code 1)
out data_ostd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Decoded / corrected data.
in payloadData_istd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Message to be decoded.
in fecData_istd_logic_vector%(%((N%-%K)%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
FEC USEd to decode.
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code3_s
FEC12 decoded data (code 3)
in bypassstd_logic%
Bypass uplink FEC (test purpose only)
rs_decoder_N31K29 - N31K29 Reed-Solomon decoder
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code4_s
FEC12 decoded data (code 4)
lpgbtfpga_decoder - Uplink FEC decoder
out data_ostd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Decoded / corrected data.
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code1_s
FEC12 encoded data (code 1)
in fec5_fec_istd_logic_vector%(%19%%%downto%%%0%)
FEC input from de-interleaver for FEC5 decoding (redundant on upper/lower part of the bus @5...
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code3_s
FEC12 encoded data (code 3)
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.
std_logic_vector%(%144%%%downto%%%0%)% fec5_encoded_code1_s
FEC5 encoded data (code 1)
in fecData_istd_logic_vector%(%((N%-%K)%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
FEC USEd to decode.
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code1_s
FEC12 decoded data (code 1)
std_logic_vector%(%205%%%downto%%%0%)% fec12_data_s
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
std_logic_vector%(%144%%%downto%%%0%)% fec5_encoded_code0_s
FEC5 encoded data (code 0)
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code0_s
FEC12 encoded data (code 0)
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code5_s
FEC12 encoded data (code 5)
in fec5_data_istd_logic_vector%(%233%%%downto%%%0%)
Data input from de-interleaver for FEC5 decoding (redundant on upper/lower part of the bus @5...
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code4_s
FEC12 encoded data (code 4)
DATARATEinteger%range%0%%%to%%%2
Datarate selection can be: DATARATE_10G24 or DATARATE_5G12.
std_logic_vector%(%144%%%downto%%%0%)% fec5_decoded_code0_s
FEC5 decoded data (code 0)
std_logic_vector%(%205%%%downto%%%0%)% fec12_toenc_data_s
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
out fec12_data_ostd_logic_vector%(%205%%%downto%%%0%)
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code5_s
FEC12 decoded data (code 5)
FECinteger%range%0%%%to%%%2
FEC selection can be: FEC5 or FEC12.
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code2_s
FEC12 encoded data (code 2)
in fec12_data_istd_logic_vector%(%205%%%downto%%%0%)
Data input from de-interleaver for FEC12 decoding (redundant on upper/lower part of the bus @5...
in fec12_fec_istd_logic_vector%(%47%%%downto%%%0%)
FEC input from de-interleaver for FEC12 decoding (redundant on upper/lower part of the bus @5...
out fec5_data_ostd_logic_vector%(%233%%%downto%%%0%)
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...