lpgbtfpga_rxgearbox.vhd
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1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 USE ieee.numeric_std.all;
12 
22  GENERIC (
23  c_clockRatio : integer;
24  c_inputWidth : integer;
25  c_outputWidth : integer;
26  c_counterInitValue : integer := 2
27  );
28  PORT (
29  -- Clock and reset
30  clk_inClk_i : in std_logic;
31  clk_outClk_i : in std_logic;
32  clk_clkEn_i : in std_logic;
33  clk_dataFlag_o : out std_logic;
34 
35  rst_gearbox_i : in std_logic;
36 
37  -- Data
38  dat_inFrame_i : in std_logic_vector((c_inputWidth-1) downto 0);
39  dat_outFrame_o : out std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0);
40 
41  -- Status
42  sta_gbRdy_o : out std_logic
43  );
44 END lpgbtfpga_rxGearbox;
45 
51 ARCHITECTURE behavioral OF lpgbtfpga_rxGearbox IS
52 
53  --==================================== User Logic =====================================--
54  CONSTANT c_oversampling : integer := c_clockRatio/(c_outputWidth/c_inputWidth);
55 
56  SIGNAL reg0 : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
57  SIGNAL reg1 : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
58  SIGNAL rxFrame_inverted_s : std_logic_vector (((c_inputWidth*c_clockRatio)-1) downto 0);
59 
60  SIGNAL gbReset_s : std_logic;
61  SIGNAL sta_gbRdy_s0 : std_logic;
62  SIGNAL sta_gbRdy_s : std_logic;
63  SIGNAL clk_dataFlag_s : std_logic;
64 
65  SIGNAL dat_outFrame_s : std_logic_vector((c_inputWidth*c_clockRatio)-1 downto 0);
66 
67  SIGNAL dat_inFrame_s : std_logic_vector((c_inputWidth-1) downto 0);
68 
69  SIGNAL gbReset_outsynch_s : std_logic;
70  --=====================================================================================--
71 
72 --=================================================================================================--
73 BEGIN --========#### Architecture Body ####========--
74 --=================================================================================================--
75 
76  gbRstSynch_proc: PROCESS(rst_gearbox_i, clk_inClk_i)
77  BEGIN
78 
79  IF rst_gearbox_i = '1' THEN
80  gbReset_s <= '1';
81 
82  ELSIF rising_edge(clk_inClk_i) THEN
83 
84  IF clk_clkEn_i = '1' THEN
85  gbReset_s <= '0';
86  END IF;
87 
88  END IF;
89  END PROCESS;
90 
91  rxWordPipeline_proc: PROCESS(gbReset_s, clk_inClk_i)
92  BEGIN
93  IF gbReset_s = '1' THEN
94  dat_inFrame_s <= (OTHERS => '0');
95  ELSIF rising_edge(clk_inClk_i) THEN
96  dat_inFrame_s <= dat_inFrame_i;
97  END IF;
98  END PROCESS;
99 
100 
101  gbRegMan_proc: PROCESS(gbReset_s, clk_inClk_i)
102  VARIABLE cnter : integer RANGE 0 to c_clockRatio;
103  BEGIN
104 
105  IF gbReset_s = '1' THEN
106  reg0 <= (OTHERS => '0');
107  reg1 <= (OTHERS => '0');
108  sta_gbRdy_s0 <= '0';
109 
110  cnter := c_counterInitValue;
111 
112  ELSIF rising_edge(clk_inClk_i) THEN
113  clk_dataFlag_s <= '0';
114 
115  IF cnter = 0 THEN
116  reg1 <= reg0;
117  clk_dataFlag_s <= '1';
118  sta_gbRdy_s0 <= '1';
119  sta_gbRdy_s <= sta_gbRdy_s0; --Delay ready for 1 word. First word could be corrupted
120  END IF;
121 
122  reg0((c_inputWidth*(1+cnter))-1 downto (c_inputWidth*cnter)) <= dat_inFrame_s;
123  cnter := cnter + 1;
124 
125  IF cnter = c_clockRatio THEN
126  cnter := 0;
127  END IF;
128  END IF;
129 
130  END PROCESS;
131 
132  frameInverter: FOR i IN ((c_inputWidth*c_clockRatio)-1) downto 0 GENERATE
133  rxFrame_inverted_s(i) <= reg1(((c_inputWidth*c_clockRatio)-1)-i);
134  END GENERATE;
135 
136  oversamplerMultPh: FOR i IN 0 TO (c_oversampling-1) GENERATE
137  oversamplerPhN: FOR j IN 0 TO (c_outputWidth-1) GENERATE
138  dat_outFrame_s((i*c_outputWidth)+j) <= rxFrame_inverted_s((j*c_oversampling)+i);
139  END GENERATE;
140  END GENERATE;
141 
142  -- Pipeline dat_outFrame_o to avoid clocking issue
143  clkEnPipeline_proc: PROCESS(clk_outClk_i)
144  BEGIN
145  IF rising_edge(clk_outClk_i) THEN
146  gbReset_outsynch_s <= gbReset_s;
147  END IF;
148  END PROCESS;
149 
150  outPipeline_proc: PROCESS(gbReset_outsynch_s, clk_outClk_i)
151  BEGIN
152  IF gbReset_outsynch_s = '1' THEN
153  dat_outFrame_o <= (OTHERS => '0');
154  clk_dataFlag_o <= '0';
155  sta_gbRdy_o <= '0';
156 
157  ELSIF rising_edge(clk_outClk_i) THEN
158 
159  clk_dataFlag_o <= clk_dataFlag_s;
160  dat_outFrame_o <= dat_outFrame_s;
161  sta_gbRdy_o <= sta_gbRdy_s;
162 
163  END IF;
164  END PROCESS;
165  --=====================================================================================--
166 END behavioral;
167 --=================================================================================================--
168 --#################################################################################################--
169 --=================================================================================================--
out dat_outFrame_ostd_logic_vector%(%(c_inputWidth%*%c_clockRatio)%-%1%%%downto%%%0%)
Output data, concatenation of word WHEN the word ratio is lower than clock ration (e...
in rst_gearbox_istd_logic%
Reset SIGNAL.
c_clockRatiointeger%
Clock ratio is clock_out / clock_in (shall be an integer)
in clk_clkEn_istd_logic%
Clock enable (e.g.: header flag)
c_outputWidthinteger%
Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer) ...
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.
in dat_inFrame_istd_logic_vector%(%(c_inputWidth%-%1)%%%downto%%%0%)
Input data from MGT.
in clk_inClk_istd_logic%
Input clock (from MGT)
in clk_outClk_istd_logic%
Output clock (from MGT)
c_inputWidthinteger%
Bus size of the input word.
c_counterInitValueinteger%:=2
Initialization value of the gearbox counter (3 for simulation / 2 for real HW)
lpgbtfpga_rxGearbox - Rx Gearbox
out sta_gbRdy_ostd_logic%
Ready SIGNAL.