lpgbtfpga_framealigner Entity Reference

lpgbtfpga_framealigner - MGT word aligner (Pattern search) More...

Inheritance diagram for lpgbtfpga_framealigner:
lpgbtfpga_uplink

Detailed Description

lpgbtfpga_framealigner - MGT word aligner (Pattern search)

The lpgbtfpga_framealigner module ask for clock shift to align the frame header.

Definition at line 20 of file lpgbtfpga_framealigner.vhd.


The documentation for this class was generated from the following file:

Entities

behavioral  architecture
 lpgbtfpga_framealigner - MGT word aligner (Pattern search) More...
 

Libraries

ieee 
 Include the IEEE VHDL standard LIBRARY.

Use Clauses

ieee.std_logic_1164.all 
ieee.numeric_std.all 
work.lpgbtfpga_package.all 
 Include the lpGBT-FPGA specific package.

Generics

c_wordRatio  integer
 Word ration: frameclock / mgt_wordclock.
c_wordSize  integer
 Size of the mgt word.
c_headerPattern  std_logic_vector
 Header pattern specified by the standard.
c_allowedFalseHeader  integer
 Number of false header allowed to avoid unlock on frame error.
c_allowedFalseHeaderOverN  integer
 Number of header checked to know wether the lock is lost or not.
c_requiredTrueHeader  integer
 Number of true header required to go in locked state.
c_bitslip_mindly  integer := 1
 Number of clock cycle required WHEN asserting the bitslip SIGNAL.
c_bitslip_waitdly  integer := 40
 Number of clock cycle required before being back in a stable state.

Ports

clk_pcsRx_i   in std_logic
 MGT Wordclock.
rst_pattsearch_i   in std_logic
 Rst the pattern search state machines.
cmd_bitslipCtrl_o   out std_logic
 Bitslip SIGNAL to shift the parrallel word.
sta_headerLocked_o   out std_logic
 Status: header is locked.
sta_headerFlag_o   out std_logic
 Status: header flag (1 pulse over c_wordRatio)
sta_bitSlipEven_o   out std_logic
 Status: number of bit slips is even.
dat_word_i   in std_logic_vector ( c_headerPattern ' length - 1 downto 0 )
 Header bits from the MGT word (compared with c_headerPattern)