lpgbtfpga_rxGearbox Entity Reference

lpgbtfpga_rxGearbox - Rx Gearbox More...

Inheritance diagram for lpgbtfpga_rxGearbox:
lpgbtfpga_uplink

Detailed Description

lpgbtfpga_rxGearbox - Rx Gearbox

The Rx gearbox module is USEd to ensure the MGT to Datapath clock domain crossing. It takes the c_inputWidth bit words in input and generates an c_outputWidth bit word every c_clockRatio clock cycle. When the clock ratio is bigger than the word ratio (oversampling), each word get from each phase is stored in different words that are concatenated and set in output. E.g.: (A0)(A1)(B0)(B1)(C0)(C1) where (A0) and (A1) are the "same bit" (2 samples took by the MGT in the same UI, becaUSE of the oversampling), the output is (A0)(B0)(C0)(A1)(B1)(B1).

Definition at line 21 of file lpgbtfpga_rxgearbox.vhd.


The documentation for this class was generated from the following file:

Entities

behavioral  architecture
 lpgbtfpga_rxGearbox - Rx Gearbox More...
 

Libraries

ieee 
 Include the IEEE VHDL standard LIBRARY.

Use Clauses

ieee.std_logic_1164.all 
ieee.numeric_std.all 

Generics

c_clockRatio  integer
 Clock ratio is clock_out / clock_in (shall be an integer)
c_inputWidth  integer
 Bus size of the input word.
c_outputWidth  integer
 Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer)
c_counterInitValue  integer := 2
 Initialization value of the gearbox counter (3 for simulation / 2 for real HW)

Ports

clk_inClk_i   in std_logic
 Input clock (from MGT)
clk_outClk_i   in std_logic
 Output clock (from MGT)
clk_clkEn_i   in std_logic
 Clock enable (e.g.: header flag)
clk_dataFlag_o   out std_logic
rst_gearbox_i   in std_logic
 Reset SIGNAL.
dat_inFrame_i   in std_logic_vector ( ( c_inputWidth - 1 ) downto 0 )
 Input data from MGT.
dat_outFrame_o   out std_logic_vector ( ( c_inputWidth * c_clockRatio ) - 1 downto 0 )
 Output data, concatenation of word WHEN the word ratio is lower than clock ration (e.g.: out <= word & word;)
sta_gbRdy_o   out std_logic
 Ready SIGNAL.