lpgbtfpga_downlink.vhd
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248 --#################################################################################################--
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in encoderBypass_istd_logic%
Bypass downlink FEC (test purpose only)
Definition: lpgbtfpga_downlink.vhd:44
lpgbtfpga_interleaver - Downlink data interleaver
Definition: lpgbtfpga_interleaver.vhd:19
in ECData_istd_logic_vector%(%1%%%downto%%%0%)
Downlink EC field.
Definition: lpgbtfpga_downlink.vhd:36
c_outputWidthinteger%
Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer) ...
Definition: lpgbtfpga_txgearbox.vhd:23
std_logic_vector%(%35%%%downto%%%0%)% scrambledData_s
Scrambled data.
Definition: lpgbtfpga_downlink.vhd:139
c_clockRatiointeger%
Clock ratio is clock_out / clock_in (shall be an integer)
Definition: lpgbtfpga_txgearbox.vhd:21
lpgbtfpga_interleaver lpgbtfpga_interleaver_instlpgbtfpga_interleaver_inst
Interleaver Used to improve the decoding efficiency.
Definition: lpgbtfpga_downlink.vhd:207
in clk_istd_logic%
Downlink datapath clock (Transceiver Tx User clock, typically 320MHz)
Definition: lpgbtfpga_downlink.vhd:30
in clk_clkEn_istd_logic%
Input clock enable WHEN multicycle path or '1'.
Definition: lpgbtfpga_txgearbox.vhd:28
lpgbtfpga_encoder lpgbtfpga_encoder_instlpgbtfpga_encoder_inst
FEC calculator Used for the downlink encoding.
Definition: lpgbtfpga_downlink.vhd:196
c_outputWidthinteger%
Transceiver's word size (Typically 32 bits)
Definition: lpgbtfpga_downlink.vhd:26
in interleaverBypass_istd_logic%
Bypass downlink interleaver (test purpose only)
Definition: lpgbtfpga_downlink.vhd:43
Definition: lpgbtfpga_package.vhd:13
lpgbtfpga_downlink - Downlink wrapper (top level)
Definition: lpgbtfpga_downlink.vhd:21
in dat_inFrame_istd_logic_vector%(%(c_inputWidth%-%1)%%%downto%%%0%)
Input data.
Definition: lpgbtfpga_txgearbox.vhd:34
out mgt_word_ostd_logic_vector%(%(c_outputWidth%-%1)%%%downto%%%0%)
Downlink encoded frame (IC + EC + User Data + FEC)
Definition: lpgbtfpga_downlink.vhd:40
in scramblerBypass_istd_logic%
Bypass downlink scrambler (test purpose only)
Definition: lpgbtfpga_downlink.vhd:45
std_logic_vector%(%35%%%downto%%%0%)% inputData_s
Data bus made of IC + EC + User Data (Used to input the scrambler)
Definition: lpgbtfpga_downlink.vhd:138
in clkEn_istd_logic%
Clock enable (1 pulse over 8 clock cycles when encoding runs @ 320Mhz)
Definition: lpgbtfpga_downlink.vhd:31
lpgbtfpga_scrambler lpgbtfpga_scrambler_instlpgbtfpga_scrambler_inst
Scrambler module Used for the downlink encoding.
Definition: lpgbtfpga_downlink.vhd:182
in rst_n_istd_logic%
Downlink reset SIGNAL (Tx ready from the transceiver)
Definition: lpgbtfpga_downlink.vhd:32
c_clockRatiointeger%:=8
Clock ratio is clock_out / 40 (shall be an integer - E.g.: 320/40 = 8)
Definition: lpgbtfpga_downlink.vhd:25
in userData_istd_logic_vector%(%31%%%downto%%%0%)
Downlink data (User)
Definition: lpgbtfpga_downlink.vhd:35
in ICData_istd_logic_vector%(%1%%%downto%%%0%)
Downlink IC field.
Definition: lpgbtfpga_downlink.vhd:37
lpgbtfpga_scrambler - 36bit Order 36 scrambler
Definition: lpgbtfpga_scrambler.vhd:16
out dat_outFrame_ostd_logic_vector%(%(c_outputWidth%-%1)%%%downto%%%0%)
Output data.
Definition: lpgbtfpga_txgearbox.vhd:35
lpgbtfpga_txGearbox lpgbtfpga_txgearbox_instlpgbtfpga_txgearbox_inst
Bridge between frame word and MGT word.
Definition: lpgbtfpga_downlink.vhd:225
c_multicyleDelayinteger%range%0%%%to%%%7:=3
Multicycle delay: Used to relax the timing constraints.
Definition: lpgbtfpga_downlink.vhd:24