lpgbtfpga_downlink.vhd
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1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 
13 USE work.lpgbtfpga_package.all;
14 
22  GENERIC(
23  -- Expert parameters
24  c_multicyleDelay : integer RANGE 0 to 7 := 3;
25  c_clockRatio : integer := 8;
26  c_outputWidth : integer
27  );
28  PORT (
29  -- Clocks
30  clk_i : in std_logic;
31  clkEn_i : in std_logic;
32  rst_n_i : in std_logic;
33 
34  -- Down link
35  userData_i : in std_logic_vector(31 downto 0);
36  ECData_i : in std_logic_vector(1 downto 0);
37  ICData_i : in std_logic_vector(1 downto 0);
38 
39  -- Output
40  mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0);
41 
42  -- Configuration
43  interleaverBypass_i : in std_logic;
44  encoderBypass_i : in std_logic;
45  scramblerBypass_i : in std_logic;
46 
47  -- Status
48  rdy_o : out std_logic
49  );
50 END lpgbtfpga_downlink;
51 
58 ARCHITECTURE behavioral OF lpgbtfpga_downlink IS
59 
62  GENERIC (
63  INIT_SEED : in std_logic_vector(35 downto 0) := x"1fba847af"
64  );
65  PORT (
66  -- Clocks & reset
67  clk_i : in std_logic;
68  clkEn_i : in std_logic;
69 
70  reset_i : in std_logic;
71 
72  -- Data
73  data_i : in std_logic_vector(35 downto 0);
74  data_o : out std_logic_vector(35 downto 0);
75 
76  -- Control
77  bypass : in std_logic
78  );
79  END COMPONENT;
80 
82  COMPONENT lpgbtfpga_encoder IS
83  PORT (
84  -- Data
85  data_i : in std_logic_vector(35 downto 0);
86  FEC_o : out std_logic_vector(23 downto 0);
87 
88  -- Control
89  bypass : in std_logic
90  );
91  END COMPONENT;
92 
94  COMPONENT lpgbtfpga_interleaver IS
95  GENERIC(
96  HEADER_c : in std_logic_vector(3 downto 0)
97  );
98  PORT (
99  -- Data
100  data_i : in std_logic_vector(35 downto 0);
101  FEC_i : in std_logic_vector(23 downto 0);
102 
103  data_o : out std_logic_vector(63 downto 0);
104 
105  -- Control
106  bypass : in std_logic
107  );
108  END COMPONENT;
109 
111  GENERIC (
112  c_clockRatio : integer;
113  c_inputWidth : integer;
114  c_outputWidth : integer
115  );
116  PORT (
117  -- Clock and reset
118  clk_inClk_i : in std_logic;
119  clk_clkEn_i : in std_logic;
120  clk_outClk_i : in std_logic;
121 
122  rst_gearbox_i : in std_logic;
123 
124  -- Data
125  dat_inFrame_i : in std_logic_vector((c_inputWidth-1) downto 0);
126  dat_outFrame_o : out std_logic_vector((c_outputWidth-1) downto 0);
127 
128  -- Status
129  sta_gbRdy_o : out std_logic
130  );
131  END COMPONENT;
132 
133  SIGNAL rst_s : std_logic;
134  SIGNAL gbRst_s : std_logic;
135  SIGNAL gbRdy_s : std_logic;
136  SIGNAL encodedFrame_s : std_logic_vector(63 downto 0);
137 
138  SIGNAL inputData_s : std_logic_vector(35 downto 0);
139  SIGNAL scrambledData_s : std_logic_vector(35 downto 0);
140  SIGNAL FECData_s : std_logic_vector(23 downto 0);
141  SIGNAL clkOutEn_s : std_logic;
142  SIGNAL rst_synch_s : std_logic;
143 BEGIN --========#### Architecture Body ####========-
144 
145  rst_s <= not(gbRdy_s);
146  gbRst_s <= not(rst_n_i);
147 
150  VARIABLE cnter : integer RANGE 0 TO 7;
151  BEGIN
152 
153  IF rst_s = '1' THEN
154  cnter := 0;
155  clkOutEn_s <= '0';
156  rst_synch_s <= '0';
157 
158  ELSIF rising_edge(clk_i) THEN
159  IF clkEn_i = '1' THEN
160  cnter := 0;
161  rst_synch_s <= '1';
162  ELSIF rst_synch_s = '1' THEN
163  if(cnter < 7) then
164  cnter := cnter + 1;
165  else
166  cnter := 0;
167  end if;
168  END IF;
169 
170  clkOutEn_s <= '0';
171  IF cnter = c_multicyleDelay THEN
172  clkOutEn_s <= '1';
173  END IF;
174  END IF;
175  END PROCESS;
176 
177  inputData_s(31 downto 0) <= userData_i;
178  inputData_s(33 downto 32) <= ECData_i;
179  inputData_s(35 downto 34) <= ICData_i;
180 
183  PORT MAP (
184  clk_i => clk_i,
185  clkEn_i => clkOutEn_s,
186 
187  reset_i => rst_s,
188 
189  data_i => inputData_s,
190  data_o => scrambledData_s ,
191 
192  bypass => scramblerBypass_i
193  );
194 
197  PORT MAP (
198  -- Data
199  data_i => scrambledData_s ,
200  FEC_o => FECData_s,
201 
202  -- Control
203  bypass => encoderBypass_i
204  );
205 
208  GENERIC MAP (
209  HEADER_c => "1001"
210  )
211  PORT MAP (
212  -- Data
213  data_i => scrambledData_s ,
214  FEC_i => FECData_s,
215 
216  data_o => encodedFrame_s ,
217 
218  -- Control
219  bypass => interleaverBypass_i
220  );
221 
222  rdy_o <= rst_synch_s;
223 
226  GENERIC MAP(
228  c_inputWidth => 64,
230  )
231  PORT MAP(
232  -- Clock and reset
233  clk_inClk_i => clk_i,
234  clk_clkEn_i => clkEn_i,
235  clk_outClk_i => clk_i,
236 
237  rst_gearbox_i => gbRst_s,
238 
239  -- Data
240  dat_inFrame_i => encodedFrame_s,
242 
243  -- Status
244  sta_gbRdy_o => gbRdy_s
245  );
246 END behavioral;
247 --=================================================================================================--
248 --#################################################################################################--
249 --=================================================================================================--
in rst_gearbox_istd_logic%
Reset SIGNAL.
lpgbtfpga_interleaver - Downlink data interleaver
c_outputWidthinteger%
Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer) ...
c_clockRatiointeger%
Clock ratio is clock_out / clock_in (shall be an integer)
lpgbtfpga_encoder - Downlink FEC encoder
in clk_clkEn_istd_logic%
Input clock enable WHEN multicycle path or &#39;1&#39;.
in dat_inFrame_istd_logic_vector%(%(c_inputWidth%-%1)%%%downto%%%0%)
Input data.
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.
lpgbtfpga_scrambler - 36bit Order 36 scrambler
in clk_inClk_istd_logic%
Input clock (frame clock)
in clk_outClk_istd_logic%
Output clock (from the MGT)
c_inputWidthinteger%
Bus size of the input word.
out dat_outFrame_ostd_logic_vector%(%(c_outputWidth%-%1)%%%downto%%%0%)
Output data.
out sta_gbRdy_ostd_logic%
Ready SIGNAL.
lpgbtfpga_txGearbox - Tx Gearbox