lpgbtfpga_txgearbox.vhd
Go to the documentation of this file.
64 --=================================================================================================--
66 --=================================================================================================--
75 -- Comment: Note!! The reset of the gearbox is synchronous to TX_FRAMECLK in order to align the address 0
119 txWord_beforeOversampling_s <= txFrame_from_frameInverter_pipe_s((c_inputWidth/c_clockRatio)-1 downto 0);
122 txWord_beforeOversampling_s <= txFrame_from_frameInverter_reg_s(((c_inputWidth/c_clockRatio)*(address+1))-1 downto ((c_inputWidth/c_clockRatio)*(address)));
149 --=================================================================================================--
150 --#################################################################################################--
151 --=================================================================================================--
c_outputWidthinteger%
Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer) ...
Definition: lpgbtfpga_txgearbox.vhd:23
c_clockRatiointeger%
Clock ratio is clock_out / clock_in (shall be an integer)
Definition: lpgbtfpga_txgearbox.vhd:21
in clk_clkEn_istd_logic%
Input clock enable WHEN multicycle path or '1'.
Definition: lpgbtfpga_txgearbox.vhd:28
in dat_inFrame_istd_logic_vector%(%(c_inputWidth%-%1)%%%downto%%%0%)
Input data.
Definition: lpgbtfpga_txgearbox.vhd:34
out dat_outFrame_ostd_logic_vector%(%(c_outputWidth%-%1)%%%downto%%%0%)
Output data.
Definition: lpgbtfpga_txgearbox.vhd:35