behavioral Architecture Reference
lpgbtfpga_decoder - Uplink FEC decoder More...
Detailed Description
lpgbtfpga_decoder - Uplink FEC decoder
The lpgbtfpga_decoder module instantiates the Reed-Solomon N31K29 and N15K13 modules to correct errors for both FEC5 and FEC12 configuration. Only the required logic is USEd WHEN the DATARATE is configured to run at 5.12gbps.
Definition at line 50 of file lpgbtfpga_decoder.vhd.
The documentation for this class was generated from the following files:
- /mnt/lpgbt-fpga-sources/uplink/lpgbtfpga_decoder.vhd
Processes | |
| PROCESS_1 | ( uplinkClk_i ) |
Components | |
| rs_decoder_N31K29 | <Entity rs_decoder_N31K29> |
| rs_decoder_N15K13 | <Entity rs_decoder_N15K13> |
Signals | |
| fec5_encoded_code0_s | std_logic_vector ( 144 downto 0 ) |
| FEC5 encoded data (code 0) | |
| fec5_encoded_code1_s | std_logic_vector ( 144 downto 0 ) |
| FEC5 encoded data (code 1) | |
| fec5_decoded_code0_s | std_logic_vector ( 144 downto 0 ) |
| FEC5 decoded data (code 0) | |
| fec5_decoded_code1_s | std_logic_vector ( 144 downto 0 ) |
| FEC5 decoded data (code 1) | |
| fec12_encoded_code0_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 0) | |
| fec12_encoded_code1_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 1) | |
| fec12_encoded_code2_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 2) | |
| fec12_encoded_code3_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 3) | |
| fec12_encoded_code4_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 4) | |
| fec12_encoded_code5_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 encoded data (code 5) | |
| fec12_decoded_code0_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 0) | |
| fec12_decoded_code1_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 1) | |
| fec12_decoded_code2_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 2) | |
| fec12_decoded_code3_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 3) | |
| fec12_decoded_code4_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 4) | |
| fec12_decoded_code5_s | std_logic_vector ( 51 downto 0 ) |
| FEC12 decoded data (code 5) | |
| fec5_data_s | std_logic_vector ( 233 downto 0 ) |
| Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) | |
| fec5_toenc_data_s | std_logic_vector ( 233 downto 0 ) |
| Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) | |
| fec12_data_s | std_logic_vector ( 205 downto 0 ) |
| Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) | |
| fec12_toenc_data_s | std_logic_vector ( 205 downto 0 ) |
| Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) | |
Instantiations | |
| rs_decoder_n31k29_c0_inst | rs_decoder_N31K29 <Entity rs_decoder_N31K29> |
| rs_decoder_n31k29_c1_inst | rs_decoder_N31K29 <Entity rs_decoder_N31K29> |
| rs_decoder_n15k13_c0_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
| rs_decoder_n15k13_c1_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
| rs_decoder_n15k13_c2_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
| rs_decoder_n15k13_c3_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
| rs_decoder_n15k13_c4_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
| rs_decoder_n15k13_c5_inst | rs_decoder_N15K13 <Entity rs_decoder_N15K13> |
