behavioral Architecture Reference
lpgbtfpga_uplink - Uplink wrapper (top level) More...
Detailed Description
lpgbtfpga_uplink - Uplink wrapper (top level)
The lpgbtfpga_uplink module receives the data from the transceiver and decode them to generate the User frame. It supports the 4 following configurations:
- *(FEC5 / 5.12 Gbps)*: User data output is 112bit (can correct up to 5 consecutives bits)
- *(FEC12 / 5.12 Gbps)*: User data output is 98bit (can correct up to 12 consecutives bits)
- *(FEC5 / 10.24 Gbps)*: User data output is 230bit (can correct up to 10 consecutives bits)
- *(FEC12 / 10.24 Gbps)*: User data output is 202bit (can correct up to 24 consecutives bits)
Definition at line 82 of file lpgbtfpga_uplink.vhd.
The documentation for this class was generated from the following files:
- /mnt/lpgbt-fpga-sources/lpgbtfpga_uplink.vhd
Processes | |
| dataInPipeliner_proc | ( uplinkClk_i , datapath_rst_s ) |
| Data input pipeline. | |
| syncShIFtReg_proc | ( datapath_rst_s , uplinkClk_i ) |
| Multicycle path configuration. | |
| readySync_proc | ( uplinkClk_i , datapath_rst_s ) |
| Generate ready SIGNAL from the reset (2 clock cycle delay) | |
Components | |
| lpgbtfpga_framealigner | <Entity lpgbtfpga_framealigner> |
| Word ration: frameclock / mgt_wordclock. | |
| lpgbtfpga_rxGearbox | <Entity lpgbtfpga_rxGearbox> |
| Header bits from the MGT word (compared with c_headerPattern) | |
| lpgbtfpga_deinterleaver | <Entity lpgbtfpga_deinterleaver> |
| Ready SIGNAL. | |
| lpgbtfpga_decoder | <Entity lpgbtfpga_decoder> |
| Uplink de-interleaver component. | |
| lpgbtfpga_descrambler | <Entity lpgbtfpga_descrambler> |
| Uplink decoder component. | |
Signals | |
| sta_headerFlag_s | std_logic |
| sta_dataflag_s | std_logic |
| rst_gearbox_s | std_logic |
| sta_headerLocked_s | std_logic |
| gbxFrame_s | std_logic_vector ( 255 downto 0 ) |
| gbxFrame_5g12_s | std_logic_vector ( 127 downto 0 ) |
| sta_gbRdy_s | std_logic |
| rst_pattsearch_s | std_logic |
| datapath_rst_s | std_logic |
| fec5_data_from_deinterleaver_s | std_logic_vector ( 233 downto 0 ) |
| Data from de-interleaver (FEC5) | |
| fec5_fec_from_deinterleaver_s | std_logic_vector ( 19 downto 0 ) |
| FEC from de-interleaver (FEC5) | |
| fec12_data_from_deinterleaver_s | std_logic_vector ( 205 downto 0 ) |
| Data from de-interleaver (FEC12) | |
| fec12_fec_from_deinterleaver_s | std_logic_vector ( 47 downto 0 ) |
| FEC from de-interleaver (FEC12) | |
| fec5_data_from_decoder_s | std_logic_vector ( 233 downto 0 ) |
| Data from decoder (FEC5) | |
| fec12_data_from_decoder_s | std_logic_vector ( 205 downto 0 ) |
| Data from decoder (FEC12) | |
| fec5_data_from_descrambler_s | std_logic_vector ( 233 downto 0 ) |
| Data from descrambler (FEC5) | |
| fec12_data_from_descrambler_s | std_logic_vector ( 205 downto 0 ) |
| Data from descrambler (FEC12) | |
| fec5_correction_s | std_logic_vector ( 233 downto 0 ) |
| Correction flag (FEC5) | |
| fec12_correction_s | std_logic_vector ( 205 downto 0 ) |
| Correction flag (FEC12) | |
| rdy_0_s | std_logic |
| Ready register to delay the ready SIGNAL. | |
| rdy_1_s | std_logic |
| Ready register to delay the ready SIGNAL. | |
| UserData_10g24_s | std_logic_vector ( 229 downto 0 ) |
| Uplink output for 10g24 datarate configuration (User data) | |
| EcData_10g24_s | std_logic_vector ( 1 downto 0 ) |
| Uplink output for 10g24 datarate configuration (EC) | |
| IcData_10g24_s | std_logic_vector ( 1 downto 0 ) |
| Uplink output for 10g24 datarate configuration (IC) | |
| UserData_5g12_s | std_logic_vector ( 229 downto 0 ) |
| Uplink output for 5g12 datarate configuration (User data) | |
| EcData_5g12_s | std_logic_vector ( 1 downto 0 ) |
| Uplink output for 5g12 datarate configuration (EC) | |
| IcData_5g12_s | std_logic_vector ( 1 downto 0 ) |
| Uplink output for 5g12 datarate configuration (IC) | |
| uplinkCorrData_10g24_s | std_logic_vector ( 229 downto 0 ) |
| Uplink correction flag output for 10g24 datarate configuration (User data) | |
| uplinkCorrEc_10g24_s | std_logic_vector ( 1 downto 0 ) |
| Uplink correction flag output for 10g24 datarate configuration (EC) | |
| uplinkCorrIc_10g24_s | std_logic_vector ( 1 downto 0 ) |
| Uplink correction flag output for 10g24 datarate configuration (IC) | |
| uplinkCorrData_5g12_s | std_logic_vector ( 229 downto 0 ) |
| Uplink correction flag output for 5g12 datarate configuration (User data) | |
| uplinkCorrEc_5g12_s | std_logic_vector ( 1 downto 0 ) |
| Uplink correction flag output for 5g12 datarate configuration (EC) | |
| uplinkCorrIc_5g12_s | std_logic_vector ( 1 downto 0 ) |
| Uplink correction flag output for 5g12 datarate configuration (IC) | |
| frame_pipelined_s | std_logic_vector ( 255 downto 0 ) |
| Store input data in register to ensure stability. | |
| clkEnOut_s | std_logic |
| rst_synch_s | std_logic |
Attributes | |
| keep | string |
| Uplink datapath. | |
| keep | frame_pipelined_s : signal is " true " |
| Avoid register optimization for multicycle writing. | |
Instantiations | |
| lpgbtfpga_framealigner_inst | lpgbtfpga_framealigner <Entity lpgbtfpga_framealigner> |
| rxgearbox_10g24_inst | lpgbtfpga_rxGearbox <Entity lpgbtfpga_rxGearbox> |
| rxgearbox_5g12_inst | lpgbtfpga_rxGearbox <Entity lpgbtfpga_rxGearbox> |
| lpgbtfpga_deinterleaver_inst | lpgbtfpga_deinterleaver <Entity lpgbtfpga_deinterleaver> |
| lpgbtfpga_decoder_inst | lpgbtfpga_decoder <Entity lpgbtfpga_decoder> |
| lpgbtfpga_descrambler_inst | lpgbtfpga_descrambler <Entity lpgbtfpga_descrambler> |
