Detailed Description

The lpgbtfpga_descrambler module restores the scrambled data using the algorithm specified by the lpGBT.

Definition at line 19 of file lpgbtfpga_descrambler.vhd.

The documentation for this class was generated from the following file:

Entities
behavioral	architecture
	lpgbtfpga_descrambler - Uplink descrambler More...

Libraries
ieee
	Include the IEEE VHDL standard LIBRARY.

Use Clauses
ieee.std_logic_1164.all
work.lpgbtfpga_package.all
	Include the lpGBT-FPGA specific package.

Generics
FEC	integer range 0 to 2
	FEC selection can be: FEC5 or FEC12.

Ports
clk_i	in std_logic
	Input clock USEd to decode the received data.
clkEn_i	in std_logic
	Clock enable USEd WHEN the input clock is different from 40MHz.
reset_i	in std_logic
	Uplink datapath's reset SIGNAL.
fec5_data_i	in std_logic_vector ( 233 downto 0 )
	FEC5 User data input from decoder (scrambled)
fec12_data_i	in std_logic_vector ( 205 downto 0 )
	FEC12 User data input from decoder (scrambled)
fec5_data_o	out std_logic_vector ( 233 downto 0 )
	FEC5 User data output (descrambled)
fec12_data_o	out std_logic_vector ( 205 downto 0 )
	FEC12 User data output (descrambled)
bypass	in std_logic
	Bypass uplink scrambler (test purpose only)

Entities