lpgbtfpga_descrambler.vhd
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1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 
13 USE work.lpgbtfpga_package.all;
14 
19 ENTITY lpgbtfpga_descrambler IS
20  GENERIC(
21  FEC : integer RANGE 0 to 2
22  );
23  PORT (
24  -- Clock and reset
25  clk_i : in std_logic;
26  clkEn_i : in std_logic;
27 
28  reset_i : in std_logic;
29 
30  -- Data
31  fec5_data_i : in std_logic_vector(233 downto 0);
32  fec12_data_i : in std_logic_vector(205 downto 0);
33 
34  fec5_data_o : out std_logic_vector(233 downto 0);
35  fec12_data_o : out std_logic_vector(205 downto 0);
36 
37  -- Control
38  bypass : in std_logic
39  );
40 END lpgbtfpga_descrambler;
41 
45 ARCHITECTURE behavioral OF lpgbtfpga_descrambler IS
46 
47 
48  -- Components declaration
49  COMPONENT descrambler60bitOrder58
50  PORT (
51  -- Clocks & reset
52  clk_i : in std_logic;
53  clkEn_i : in std_logic;
54 
55  reset_i : in std_logic;
56 
57  -- Data
58  data_i : in std_logic_vector(59 downto 0);
59  data_o : out std_logic_vector(59 downto 0);
60 
61  -- Control
62  bypass : in std_logic
63  );
64  END COMPONENT;
65 
66  COMPONENT descrambler58bitOrder58
67  PORT (
68  -- Clocks & reset
69  clk_i : in std_logic;
70  clkEn_i : in std_logic;
71 
72  reset_i : in std_logic;
73 
74  -- Data
75  data_i : in std_logic_vector(57 downto 0);
76  data_o : out std_logic_vector(57 downto 0);
77 
78  -- Control
79  bypass : in std_logic
80  );
81  END COMPONENT;
82 
83  COMPONENT descrambler51bitOrder49
84  PORT (
85  -- Clocks & reset
86  clk_i : in std_logic;
87  clkEn_i : in std_logic;
88 
89  reset_i : in std_logic;
90 
91  -- Data
92  data_i : in std_logic_vector(50 downto 0);
93  data_o : out std_logic_vector(50 downto 0);
94 
95  -- Control
96  bypass : in std_logic
97  );
98  END COMPONENT;
99 
100  COMPONENT descrambler53bitOrder49
101  PORT (
102  -- Clocks & reset
103  clk_i : in std_logic;
104  clkEn_i : in std_logic;
105 
106  reset_i : in std_logic;
107 
108  -- Data
109  data_i : in std_logic_vector(52 downto 0);
110  data_o : out std_logic_vector(52 downto 0);
111 
112  -- Control
113  bypass : in std_logic
114  );
115  END COMPONENT;
116 
117 BEGIN --========#### Architecture Body ####========--
118 
119  fec5_gen: IF FEC = FEC5 GENERATE
120 
121  -- 5.12Gbps and 10.24Gbps
122  descrambler58bitOrder58_l0_inst: descrambler58bitOrder58
123  PORT MAP (
124  -- Clocks & reset
125  clk_i => clk_i,
126  clkEn_i => clkEn_i,
127 
128  reset_i => reset_i,
129 
130  -- Data
131  data_i => fec5_data_i(57 downto 0),
132  data_o => fec5_data_o(57 downto 0),
133 
134  -- Control
135  bypass => bypass
136  );
137 
138  descrambler58bitOrder58_l1_inst: descrambler58bitOrder58
139  PORT MAP (
140  -- Clocks & reset
141  clk_i => clk_i,
142  clkEn_i => clkEn_i,
143 
144  reset_i => reset_i,
145 
146  -- Data
147  data_i => fec5_data_i(115 downto 58),
148  data_o => fec5_data_o(115 downto 58),
149 
150  -- Control
151  bypass => bypass
152  );
153 
154  -- 10.24Gbps only
155  descrambler58bitOrder58_h0_inst: descrambler58bitOrder58
156  PORT MAP (
157  -- Clocks & reset
158  clk_i => clk_i,
159  clkEn_i => clkEn_i,
160 
161  reset_i => reset_i,
162 
163  -- Data
164  data_i => fec5_data_i(173 downto 116),
165  data_o => fec5_data_o(173 downto 116),
166 
167  -- Control
168  bypass => bypass
169  );
170 
171  descrambler60bitOrder58_h1_inst: descrambler60bitOrder58
172  PORT MAP (
173  -- Clocks & reset
174  clk_i => clk_i,
175  clkEn_i => clkEn_i,
176 
177  reset_i => reset_i,
178 
179  -- Data
180  data_i => fec5_data_i(233 downto 174),
181  data_o => fec5_data_o(233 downto 174),
182 
183  -- Control
184  bypass => bypass
185  );
186 
187  END GENERATE;
188 
189  fec12_gen: IF FEC = FEC12 GENERATE
190 
191  -- 5.12Gbps and 10.24Gbps
192  descrambler51bitOrder49_l0_inst: descrambler51bitOrder49
193  PORT MAP (
194  -- Clocks & reset
195  clk_i => clk_i,
196  clkEn_i => clkEn_i,
197 
198  reset_i => reset_i,
199 
200  -- Data
201  data_i => fec12_data_i(50 downto 0),
202  data_o => fec12_data_o(50 downto 0),
203 
204  -- Control
205  bypass => bypass
206  );
207 
208  descrambler51bitOrder49_l1_inst: descrambler51bitOrder49
209  PORT MAP (
210  -- Clocks & reset
211  clk_i => clk_i,
212  clkEn_i => clkEn_i,
213 
214  reset_i => reset_i,
215 
216  -- Data
217  data_i => fec12_data_i(101 downto 51),
218  data_o => fec12_data_o(101 downto 51),
219 
220  -- Control
221  bypass => bypass
222  );
223 
224  -- 10.24Gbps only
225  descrambler51bitOrder49_h0_inst: descrambler51bitOrder49
226  PORT MAP (
227  -- Clocks & reset
228  clk_i => clk_i,
229  clkEn_i => clkEn_i,
230 
231  reset_i => reset_i,
232 
233  -- Data
234  data_i => fec12_data_i(152 downto 102),
235  data_o => fec12_data_o(152 downto 102),
236 
237  -- Control
238  bypass => bypass
239  );
240 
241  descrambler53bitOrder49_h1_inst: descrambler53bitOrder49
242  PORT MAP (
243  -- Clocks & reset
244  clk_i => clk_i,
245  clkEn_i => clkEn_i,
246 
247  reset_i => reset_i,
248 
249  -- Data
250  data_i => fec12_data_i(205 downto 153),
251  data_o => fec12_data_o(205 downto 153),
252 
253  -- Control
254  bypass => bypass
255  );
256 
257  END GENERATE;
258 
259 END behavioral;
260 --=================================================================================================--
261 --#################################################################################################--
262 --=================================================================================================--
lpgbtfpga_descrambler.bypass
in bypassstd_logic%
Bypass uplink scrambler (test purpose only)
Definition: lpgbtfpga_descrambler.vhd:38
lpgbtfpga_descrambler.fec5_data_o
out fec5_data_ostd_logic_vector%(%233%%%downto%%%0%)
FEC5 User data output (descrambled)
Definition: lpgbtfpga_descrambler.vhd:34
lpgbtfpga_descrambler
lpgbtfpga_descrambler - Uplink descrambler
Definition: lpgbtfpga_descrambler.vhd:19
descrambler51bitOrder49
descrambler51bitOrder49 - 51bit Order 49 descrambler
Definition: descrambler_51bitOrder49.vhd:16
lpgbtfpga_descrambler.fec12_data_i
in fec12_data_istd_logic_vector%(%205%%%downto%%%0%)
FEC12 User data input from decoder (scrambled)
Definition: lpgbtfpga_descrambler.vhd:32
lpgbtfpga_descrambler.FEC
FECinteger%range%0%%%to%%%2
FEC selection can be: FEC5 or FEC12.
Definition: lpgbtfpga_descrambler.vhd:21
lpgbtfpga_descrambler.fec12_data_o
out fec12_data_ostd_logic_vector%(%205%%%downto%%%0%)
FEC12 User data output (descrambled)
Definition: lpgbtfpga_descrambler.vhd:35
lpgbtfpga_descrambler.clk_i
in clk_istd_logic%
Input clock USEd to decode the received data.
Definition: lpgbtfpga_descrambler.vhd:25
lpgbtfpga_descrambler.clkEn_i
in clkEn_istd_logic%
Clock enable USEd WHEN the input clock is different from 40MHz.
Definition: lpgbtfpga_descrambler.vhd:26
lpgbtfpga_package
Definition: lpgbtfpga_package.vhd:13
descrambler53bitOrder49
descrambler53bitOrder49 - 53bit Order 49 descrambler
Definition: descrambler_53bitOrder49.vhd:16
lpgbtfpga_deinterleaver.ieee
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.
Definition: lpgbtfpga_deinterleaver.vhd:9
descrambler58bitOrder58
descrambler58bitOrder58 - 58bit Order 58 descrambler
Definition: descrambler_58bitOrder58.vhd:16
lpgbtfpga_descrambler.reset_i
in reset_istd_logic%
Uplink datapath's reset SIGNAL.
Definition: lpgbtfpga_descrambler.vhd:28
lpgbtfpga_descrambler.fec5_data_i
in fec5_data_istd_logic_vector%(%233%%%downto%%%0%)
FEC5 User data input from decoder (scrambled)
Definition: lpgbtfpga_descrambler.vhd:31
descrambler60bitOrder58
descrambler60bitOrder58 - 58bit Order 60 descrambler
Definition: descrambler_60bitOrder58.vhd:16
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