descrambler_58bitOrder58.vhd
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1 -------------------------------------------------------
6 -------------------------------------------------------
7 
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.all;
11 
13 USE work.lpgbtfpga_package.all;
14 
17  PORT (
18  -- Clocks & reset
19  clk_i : in std_logic;
20  clkEn_i : in std_logic;
21 
22  reset_i : in std_logic;
23 
24  -- Data
25  data_i : in std_logic_vector(57 downto 0);
26  data_o : out std_logic_vector(57 downto 0);
27 
28  -- Control
29  bypass : in std_logic
30  );
31 END descrambler58bitOrder58;
32 
34 ARCHITECTURE behavioral of descrambler58bitOrder58 IS
35 
36  SIGNAL memory_register : std_logic_vector(57 downto 0);
37  SIGNAL descrambledData : std_logic_vector(57 downto 0);
38 
39  attribute keep : string;
40  attribute keep of descrambledData : signal is "true";
41  attribute keep of memory_register : signal is "true";
42 
43 BEGIN --========#### Architecture Body ####========--
44 
45  -- Scrambler output register
46  reg_proc: PROCESS(clk_i)
47  BEGIN
48 
49  IF rising_edge(clk_i) THEN
50  IF reset_i = '1' THEN
51  descrambledData <= (OTHERS => '0');
52  memory_register <= (OTHERS => '0');
53 
54  ELSIF clkEn_i = '1' THEN
55  memory_register <= data_i;
56 
57  if bypass = '1' then
58  descrambledData <= data_i;
59  else
60  descrambledData(57 downto 39) <= data_i(57 downto 39) xnor data_i(18 downto 0) xnor memory_register(57 downto 39);
61  descrambledData(38 downto 0) <= data_i(38 downto 0) xnor memory_register(57 downto 19) xnor memory_register(38 downto 0);
62  end if;
63  END IF;
64 
65  END IF;
66 
67  END PROCESS;
68 
69  data_o <= descrambledData;
70 
71 END behavioral;
72 --=================================================================================================--
73 --#################################################################################################--
74 --=================================================================================================--
descrambler58bitOrder58 - 58bit Order 58 descrambler
_library_ ieeeieee
Include the IEEE VHDL standard LIBRARY.