lpgbtfpga_interleaver - Downlink data interleaver More...

Detailed Description

lpgbtfpga_interleaver - Downlink data interleaver

The lpgbtfpga_interleaver routes the data from the scrambler and the FEC to mix the symbol (C0/C1/C2/C3/C0/C1...). Therefore the protocol USEd is able to correct up to 4 times 3bit, meaning up to 12 consecutive errors. The interleaver add also the header in the frame, USEd by the receiver to align the frame.

Definition at line 41 of file lpgbtfpga_interleaver.vhd.

The documentation for this class was generated from the following file:

/mnt/lpgbt-fpga-sources/downlink/lpgbtfpga_interleaver.vhd

Signals
interleaved_data	std_logic_vector ( 63 downto 0 )

Detailed Description

Signals