lpgbtfpga_decoder.vhd
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130 fec5_encoded_code1_s <= "000000000000000000000000000000" & fec5_data_i(231 downto 117) WHEN (DATARATE = DATARATE_10G24) ELSE
152 fec12_encoded_code0_s <= "0000000000000000" & fec12_data_i(135 downto 134) & fec12_data_i(33 downto 0) WHEN (DATARATE = DATARATE_10G24) ELSE
155 fec12_encoded_code1_s <= "0000000000000000" & fec12_data_i(169 downto 168) & fec12_data_i(67 downto 34) WHEN (DATARATE = DATARATE_10G24) ELSE
158 fec12_encoded_code2_s <= "0000000000000000" & fec12_data_i(203 downto 202) & fec12_data_i(101 downto 68) WHEN (DATARATE = DATARATE_10G24) ELSE
193 fec12_encoded_code3_s <= "000000000000000000" & fec12_data_i(205 downto 204) & fec12_data_i(133 downto 102) WHEN (DATARATE = DATARATE_10G24) ELSE
196 fec12_encoded_code4_s <= "00000000000000000000" & fec12_data_i(167 downto 136) WHEN (DATARATE = DATARATE_10G24) ELSE
199 fec12_encoded_code5_s <= "00000000000000000000" & fec12_data_i(201 downto 170) WHEN (DATARATE = DATARATE_10G24) ELSE
331 --=================================================================================================--
332 --#################################################################################################--
333 --=================================================================================================--
std_logic_vector%(%233%%%downto%%%0%)% fec5_toenc_data_s
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:105
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code0_s
FEC12 decoded data (code 0)
Definition: lpgbtfpga_decoder.vhd:97
std_logic_vector%(%233%%%downto%%%0%)% fec5_data_s
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:104
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code2_s
FEC12 decoded data (code 2)
Definition: lpgbtfpga_decoder.vhd:99
rs_decoder_N15K13 - N15K13 Reed-Solomon decoder
Definition: fec_rsDecoderN15K13.vhd:16
in payloadData_istd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Message to be decoded.
Definition: fec_rsDecoderN15K13.vhd:23
std_logic_vector%(%144%%%downto%%%0%)% fec5_decoded_code1_s
FEC5 decoded data (code 1)
Definition: lpgbtfpga_decoder.vhd:88
out data_ostd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Decoded / corrected data.
Definition: fec_rsDecoderN15K13.vhd:26
in payloadData_istd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Message to be decoded.
Definition: fec_rsDecoderN31K29.vhd:23
in fecData_istd_logic_vector%(%((N%-%K)%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
FEC USEd to decode.
Definition: fec_rsDecoderN31K29.vhd:24
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code3_s
FEC12 decoded data (code 3)
Definition: lpgbtfpga_decoder.vhd:100
rs_decoder_N31K29 - N31K29 Reed-Solomon decoder
Definition: fec_rsDecoderN31K29.vhd:16
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code4_s
FEC12 decoded data (code 4)
Definition: lpgbtfpga_decoder.vhd:101
out data_ostd_logic_vector%(%(K%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
Decoded / corrected data.
Definition: fec_rsDecoderN31K29.vhd:26
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code1_s
FEC12 encoded data (code 1)
Definition: lpgbtfpga_decoder.vhd:91
in fec5_fec_istd_logic_vector%(%19%%%downto%%%0%)
FEC input from de-interleaver for FEC5 decoding (redundant on upper/lower part of the bus @5...
Definition: lpgbtfpga_decoder.vhd:31
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code3_s
FEC12 encoded data (code 3)
Definition: lpgbtfpga_decoder.vhd:93
std_logic_vector%(%144%%%downto%%%0%)% fec5_encoded_code1_s
FEC5 encoded data (code 1)
Definition: lpgbtfpga_decoder.vhd:85
in fecData_istd_logic_vector%(%((N%-%K)%*%SYMB_BITWIDTH)%-%1%%%downto%%%0%)
FEC USEd to decode.
Definition: fec_rsDecoderN15K13.vhd:24
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code1_s
FEC12 decoded data (code 1)
Definition: lpgbtfpga_decoder.vhd:98
Definition: lpgbtfpga_package.vhd:13
std_logic_vector%(%205%%%downto%%%0%)% fec12_data_s
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:106
std_logic_vector%(%144%%%downto%%%0%)% fec5_encoded_code0_s
FEC5 encoded data (code 0)
Definition: lpgbtfpga_decoder.vhd:84
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code0_s
FEC12 encoded data (code 0)
Definition: lpgbtfpga_decoder.vhd:90
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code5_s
FEC12 encoded data (code 5)
Definition: lpgbtfpga_decoder.vhd:95
in fec5_data_istd_logic_vector%(%233%%%downto%%%0%)
Data input from de-interleaver for FEC5 decoding (redundant on upper/lower part of the bus @5...
Definition: lpgbtfpga_decoder.vhd:30
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code4_s
FEC12 encoded data (code 4)
Definition: lpgbtfpga_decoder.vhd:94
DATARATEinteger%range%0%%%to%%%2
Datarate selection can be: DATARATE_10G24 or DATARATE_5G12.
Definition: lpgbtfpga_decoder.vhd:21
std_logic_vector%(%144%%%downto%%%0%)% fec5_decoded_code0_s
FEC5 decoded data (code 0)
Definition: lpgbtfpga_decoder.vhd:87
std_logic_vector%(%205%%%downto%%%0%)% fec12_toenc_data_s
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:107
out fec12_data_ostd_logic_vector%(%205%%%downto%%%0%)
Data output for FEC12 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:36
std_logic_vector%(%51%%%downto%%%0%)% fec12_decoded_code5_s
FEC12 decoded data (code 5)
Definition: lpgbtfpga_decoder.vhd:102
FECinteger%range%0%%%to%%%2
FEC selection can be: FEC5 or FEC12.
Definition: lpgbtfpga_decoder.vhd:22
std_logic_vector%(%51%%%downto%%%0%)% fec12_encoded_code2_s
FEC12 encoded data (code 2)
Definition: lpgbtfpga_decoder.vhd:92
in fec12_data_istd_logic_vector%(%205%%%downto%%%0%)
Data input from de-interleaver for FEC12 decoding (redundant on upper/lower part of the bus @5...
Definition: lpgbtfpga_decoder.vhd:32
in fec12_fec_istd_logic_vector%(%47%%%downto%%%0%)
FEC input from de-interleaver for FEC12 decoding (redundant on upper/lower part of the bus @5...
Definition: lpgbtfpga_decoder.vhd:33
out fec5_data_ostd_logic_vector%(%233%%%downto%%%0%)
Data output for FEC5 decoding (redundant on upper/lower part of the bus @5.12Gbps) ...
Definition: lpgbtfpga_decoder.vhd:35