lpgbtfpga_txGearbox ARCHITECTURE- Tx Gearbox More...
Detailed Description
lpgbtfpga_txGearbox ARCHITECTURE- Tx Gearbox
The txGearbox implements a register based clock domain crossing system. Using different clock for the input and output require a special attention on the phase relation between these two signals.
Definition at line 47 of file lpgbtfpga_txgearbox.vhd.
The documentation for this class was generated from the following file:
- /mnt/lpgbt-fpga-sources/downlink/lpgbtfpga_txgearbox.vhd
Processes | |
| rst_pipeline_proc | ( rst_gearbox_i , clk_inClk_i ) |
| gbRstSynch_proc | ( rst_gearbox_s , clk_outClk_i ) |
| pipeline_proc | ( clk_outClk_i ) |
| gb_proc | ( gearboxSyncReset , clk_outClk_i ) |
| PROCESS_0 | ( clk_outClk_i ) |
Constants | |
| c_oversampling | integer := c_clockRatio / ( c_inputWidth / c_outputWidth ) |
Signals | |
| gearboxSyncReset | std_logic |
| rst_gearbox_s | std_logic |
| txFrame_from_frameInverter_pipe_s | std_logic_vector ( c_inputWidth - 1 downto 0 ) |
| in_txFrame_from_frameInverter_s | std_logic_vector ( c_inputWidth - 1 downto 0 ) |
| txFrame_from_frameInverter_reg_s | std_logic_vector ( c_inputWidth - 1 downto 0 ) |
| txWord_beforeOversampling_s | std_logic_vector ( ( c_inputWidth / c_clockRatio ) - 1 downto 0 ) |
| dat_outFrame_s | std_logic_vector ( ( c_outputWidth - 1 ) downto 0 ) |
