lpgbtfpga_txGearbox Entity Reference
lpgbtfpga_txGearbox - Tx Gearbox More...
Inheritance diagram for lpgbtfpga_txGearbox:
Detailed Description
lpgbtfpga_txGearbox - Tx Gearbox
The txGearbox module implements a register based clock domain crossing system to pass from the serial clock domain to the MGT clock domain. It manages oversampling meaning that the bit are multiplicated IF the word ratio is lower than the clock ratio.
Definition at line 19 of file lpgbtfpga_txgearbox.vhd.
The documentation for this class was generated from the following file:
- /mnt/lpgbt-fpga-sources/downlink/lpgbtfpga_txgearbox.vhd
Entities | |
| behavioral | architecture |
| lpgbtfpga_txGearbox ARCHITECTURE- Tx Gearbox More... | |
Libraries | |
| ieee | |
| Include the IEEE VHDL standard LIBRARY. | |
Use Clauses | |
| ieee.std_logic_1164.all | |
| ieee.numeric_std.all | |
Generics | |
| c_clockRatio | integer |
| Clock ratio is clock_out / clock_in (shall be an integer) | |
| c_inputWidth | integer |
| Bus size of the input word. | |
| c_outputWidth | integer |
| Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer) | |
Ports | |
| clk_inClk_i | in std_logic |
| Input clock (frame clock) | |
| clk_clkEn_i | in std_logic |
| Input clock enable WHEN multicycle path or '1'. | |
| clk_outClk_i | in std_logic |
| Output clock (from the MGT) | |
| rst_gearbox_i | in std_logic |
| Reset SIGNAL. | |
| dat_inFrame_i | in std_logic_vector ( ( c_inputWidth - 1 ) downto 0 ) |
| Input data. | |
| dat_outFrame_o | out std_logic_vector ( ( c_outputWidth - 1 ) downto 0 ) |
| Output data. | |
| sta_gbRdy_o | out std_logic |
| Ready SIGNAL. | |
