lpgbtfpga_downlink Entity Reference

lpgbtfpga_downlink - Downlink wrapper (top level) More...

Inheritance diagram for lpgbtfpga_downlink:
lpgbtfpga_scrambler lpgbtfpga_encoder lpgbtfpga_interleaver lpgbtfpga_txGearbox rs_encoder_N7K5

Detailed Description

lpgbtfpga_downlink - Downlink wrapper (top level)

The lpgbtfpga_downlink module implements the logic required for the data encoding as required by the lpGBT for the downlink path (Back-END to Front-END) and split the frame to be compliant with the transceiver interface.

Definition at line 21 of file lpgbtfpga_downlink.vhd.

The documentation for this class was generated from the following file:


behavioral  architecture
 lpgbtfpga_downlink - Downlink wrapper (top level) More...


 Include the IEEE VHDL standard LIBRARY.

Use Clauses

 Include the LpGBT-FPGA specific package.


c_multicyleDelay  integer range 0 to 7 := 3
 Multicycle delay: Used to relax the timing constraints.
c_clockRatio  integer := 8
 Clock ratio is clock_out / 40 (shall be an integer - E.g.: 320/40 = 8)
c_outputWidth  integer
 Transceiver's word size (Typically 32 bits)


clk_i   in std_logic
 Downlink datapath clock (Transceiver Tx User clock, typically 320MHz)
clkEn_i   in std_logic
 Clock enable (1 pulse over 8 clock cycles when encoding runs @ 320Mhz)
rst_n_i   in std_logic
 Downlink reset SIGNAL (Tx ready from the transceiver)
userData_i   in std_logic_vector ( 31 downto 0 )
 Downlink data (User)
ECData_i   in std_logic_vector ( 1 downto 0 )
 Downlink EC field.
ICData_i   in std_logic_vector ( 1 downto 0 )
 Downlink IC field.
mgt_word_o   out std_logic_vector ( ( c_outputWidth - 1 ) downto 0 )
 Downlink encoded frame (IC + EC + User Data + FEC)
interleaverBypass_i   in std_logic
 Bypass downlink interleaver (test purpose only)
encoderBypass_i   in std_logic
 Bypass downlink FEC (test purpose only)
scramblerBypass_i   in std_logic
 Bypass downlink scrambler (test purpose only)
rdy_o   out std_logic
 Downlink ready status.