lpgbtfpga_encoder.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.lpgbtfpga_package.all;

ENTITY lpgbtfpga_encoder IS
   PORT (
        -- Data
        data_i                          : in  std_logic_vector(35 downto 0);
        FEC_o                           : out std_logic_vector(23 downto 0);

        -- Control
        bypass                          : in  std_logic
   );
END lpgbtfpga_encoder;

ARCHITECTURE behavioral OF lpgbtfpga_encoder IS

    SIGNAL virtualFrame_C0      : std_logic_vector(14 downto 0);
    SIGNAL virtualFrame_C1      : std_logic_vector(14 downto 0);
    SIGNAL virtualFrame_C2      : std_logic_vector(14 downto 0);
    SIGNAL virtualFrame_C3      : std_logic_vector(14 downto 0);

    SIGNAL FEC_s                : std_logic_vector(23 downto 0);

    COMPONENT rs_encoder_N7K5
       GENERIC (
            N                               : integer := 7;
            K                               : integer := 5;
            SYMB_BITWIDTH                   : integer := 3
       );
       PORT (
            -- Data
            msg                             : in  std_logic_vector((K*SYMB_BITWIDTH)-1 downto 0);
            parity                          : out std_logic_vector(((N-K)*SYMB_BITWIDTH)-1 downto 0)
       );
    END COMPONENT;

BEGIN                 --========####   Architecture Body   ####========--

    virtualFrame_C0 <= "000000" & data_i(8 downto 0);
    virtualFrame_C1 <= "000000" & data_i(17 downto 9);
    virtualFrame_C2 <= "000000" & data_i(26 downto 18);
    virtualFrame_C3 <= "000000" & data_i(35 downto 27);

    RSE0_inst: rs_encoder_N7K5
    PORT MAP (
        msg              => virtualFrame_C0,
        parity           => FEC_s(5 downto 0)
    );

    RSE1_inst: rs_encoder_N7K5
    PORT MAP (
        msg              => virtualFrame_C1,
        parity           => FEC_s(11 downto 6)
    );

    RSE2_inst: rs_encoder_N7K5
    PORT MAP (
        msg              => virtualFrame_C2,
        parity           => FEC_s(17 downto 12)
    );

    RSE3_inst: rs_encoder_N7K5
    PORT MAP (
        msg              => virtualFrame_C3,
        parity           => FEC_s(23 downto 18)
    );

    FEC_o   <=  FEC_s WHEN bypass = '0' ELSE (OTHERS => '0');

END behavioral;
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