rs_decoder_N31K29 ARCHITECTURE - N31K29 Reed-Solomon encoder More...
Detailed Description
rs_decoder_N31K29 ARCHITECTURE - N31K29 Reed-Solomon encoder
Definition at line 31 of file fec_rsDecoderN31K29.vhd.
The documentation for this class was generated from the following file:
- /mnt/lpgbt-fpga-sources/uplink/fec_rsDecoderN31K29.vhd
Functions | |
std_logic_vector | gf_multBy2_5 ( op: in in std_logic_vector ( 4 downto 0 ) ) |
std_logic_vector | gf_mult_5 ( op1: in in std_logic_vector ( 4 downto 0 ) , op2: in in std_logic_vector ( 4 downto 0 ) ) |
std_logic_vector | gf_inv_5 ( op: in in std_logic_vector ( 4 downto 0 ) ) |
std_logic_vector | gf_log_5 ( op: in in std_logic_vector ( 4 downto 0 ) ) |
Signals | |
msg | std_logic_vector ( ( N * SYMB_BITWIDTH ) - 1 downto 0 ) |
decMsg | std_logic_vector ( ( K * SYMB_BITWIDTH ) - 1 downto 0 ) |
outSt1 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt2 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt3 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt4 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt5 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt6 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt7 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt8 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt9 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt10 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt11 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt12 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt13 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt14 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt15 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt16 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt17 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt18 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt19 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt20 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt21 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt22 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt23 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt24 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt25 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt26 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt27 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt28 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outSt29 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd0 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd1 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd2 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd3 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd4 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd5 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd6 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd7 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd8 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd9 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd10 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd11 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd12 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd13 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd14 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd15 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd16 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd17 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd18 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd19 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd20 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd21 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd22 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd23 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd24 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd25 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd26 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd27 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outAdd28 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult0 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult1 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult2 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult3 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult4 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult5 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult6 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult7 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult8 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult9 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult10 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult11 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult12 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult13 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult14 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult15 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult16 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult17 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult18 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult19 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult20 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult21 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult22 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult23 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult24 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult25 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult26 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult27 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult28 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
outMult29 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
syndr0 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
syndr1 | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
syndr0_inv | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
syndrProd | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |
errorPos | std_logic_vector ( ( SYMB_BITWIDTH - 1 ) downto 0 ) |