lpgbtfpga_rxGearbox - Rx Gearbox More...
Detailed Description
lpgbtfpga_rxGearbox - Rx Gearbox
The rxGearbox implements a register based clock domain crossing system. Using different clock for the input and output require a special attention on the phase relation between these two signals.
Definition at line 51 of file lpgbtfpga_rxgearbox.vhd.
The documentation for this class was generated from the following file:
- /mnt/lpgbt-fpga-sources/uplink/lpgbtfpga_rxgearbox.vhd
Processes | |
| gbRstSynch_proc | ( rst_gearbox_i , clk_inClk_i ) |
| rxWordPipeline_proc | ( gbReset_s , clk_inClk_i ) |
| gbRegMan_proc | ( gbReset_s , clk_inClk_i ) |
| clkEnPipeline_proc | ( clk_outClk_i ) |
| outPipeline_proc | ( gbReset_outsynch_s , clk_outClk_i ) |
Constants | |
| c_oversampling | integer := c_clockRatio / ( c_outputWidth / c_inputWidth ) |
Signals | |
| reg0 | std_logic_vector ( ( ( c_inputWidth * c_clockRatio ) - 1 ) downto 0 ) |
| reg1 | std_logic_vector ( ( ( c_inputWidth * c_clockRatio ) - 1 ) downto 0 ) |
| rxFrame_inverted_s | std_logic_vector ( ( ( c_inputWidth * c_clockRatio ) - 1 ) downto 0 ) |
| gbReset_s | std_logic |
| sta_gbRdy_s0 | std_logic |
| sta_gbRdy_s | std_logic |
| clk_dataFlag_s | std_logic |
| dat_outFrame_s | std_logic_vector ( ( c_inputWidth * c_clockRatio ) - 1 downto 0 ) |
| dat_inFrame_s | std_logic_vector ( ( c_inputWidth - 1 ) downto 0 ) |
| gbReset_outsynch_s | std_logic |
