behavioral Architecture Reference
lpgbtfpga_deinterleaver - Uplink data de-interleaver More...
Detailed Description
lpgbtfpga_deinterleaver - Uplink data de-interleaver
The lpgbtfpga_deinterleaver routes the data from the MGT to recover the message (symbols) and FEC. It implements both FEC5 and FEC12 de-interleaver modules to reconstruct the data for both configuration.
Definition at line 43 of file lpgbtfpga_deinterleaver.vhd.
The documentation for this class was generated from the following file:
- /mnt/lpgbt-fpga-sources/uplink/lpgbtfpga_deinterleaver.vhd
Signals | |
| fec5_data_5g12_s | std_logic_vector ( 233 downto 0 ) |
| Data output for 5.12Gbps configuration. | |
| fec5_fec_5g12_s | std_logic_vector ( 19 downto 0 ) |
| FEC output for 5.12Gbps configuration. | |
| fec5_data_10g24_s | std_logic_vector ( 233 downto 0 ) |
| Data output for 10.24Gbps configuration. | |
| fec5_fec_10g24_s | std_logic_vector ( 19 downto 0 ) |
| FEC output for 10.24Gbps configuration. | |
| fec12_data_5g12_s | std_logic_vector ( 205 downto 0 ) |
| Data output for 5.12Gbps configuration. | |
| fec12_fec_5g12_s | std_logic_vector ( 47 downto 0 ) |
| FEC output for 5.12Gbps configuration. | |
| fec12_data_10g24_s | std_logic_vector ( 205 downto 0 ) |
| Data output for 10.24Gbps configuration. | |
| fec12_fec_10g24_s | std_logic_vector ( 47 downto 0 ) |
| FEC output for 10.24Gbps configuration. | |
| fec5_data_s | std_logic_vector ( 233 downto 0 ) |
| FEC5 data from de-interleaver. | |
| fec5_fec_s | std_logic_vector ( 19 downto 0 ) |
| FEC5 FEC from de-interleaver. | |
| fec12_data_s | std_logic_vector ( 205 downto 0 ) |
| FEC12 data from de-interleaver. | |
| fec12_fec_s | std_logic_vector ( 47 downto 0 ) |
| FEC12 FEC from de-interleaver. | |
