descrambler_51bitOrder49.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

USE work.lpgbtfpga_package.all;

ENTITY descrambler51bitOrder49 IS
   PORT (
        -- Clocks & reset
        clk_i                             : in  std_logic;
        clkEn_i                           : in  std_logic;

        reset_i                           : in  std_logic;

        -- Data
        data_i                            : in  std_logic_vector(50 downto 0);
        data_o                            : out std_logic_vector(50 downto 0);

        -- Control
        bypass                            : in  std_logic
   );
END descrambler51bitOrder49;

ARCHITECTURE behavioral OF descrambler51bitOrder49 IS

    SIGNAL memory_register        : std_logic_vector(50 downto 0);
    SIGNAL descrambledData        : std_logic_vector(50 downto 0);
    
    attribute keep : string;
    attribute keep of descrambledData : signal is "true";
    attribute keep of memory_register : signal is "true"; 

BEGIN                 --========####   Architecture Body   ####========--

    -- Scrambler output register
    reg_proc: PROCESS(clk_i)
    BEGIN

        IF rising_edge(clk_i) THEN
            IF reset_i = '1' THEN
                descrambledData  <= (OTHERS => '0');
                memory_register  <= (OTHERS => '0');

            ELSIF clkEn_i = '1' THEN
                memory_register               <=  data_i;

                if bypass = '1' then
                  descrambledData <= data_i;
                else
                  descrambledData(50 downto 49) <=  data_i(50 downto 49) xnor data_i(10 downto 9) xnor data_i(1 downto 0);
                  descrambledData(48 downto 40) <=  data_i(48 downto 40) xnor data_i(8 downto 0) xnor memory_register(50 downto 42);
                  descrambledData(39 downto 0)  <=  data_i(39 downto 0)  xnor memory_register(50 downto 11) xnor memory_register(41 downto 2);
                end if;

            END IF;

        END IF;

    END PROCESS;

    data_o    <= descrambledData;

END behavioral;
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